LSI版图图形编辑软件系统ZB-792

ZB-792系统是在ZB-781、ZB-791系统基础上,为适应VLSI制版需要而发展起来的版图图形编辑软件系统。它运行了操作系统RDOS支持下的DJS-130或NOVA机。     

SSTT: Efficient local search for GSI global routing

In this paper, a novel global routing algorithm is presented for congestion opti-mization based on efficient local search, named SSTT (search space traversing technology). This method manages to traverse the whole search space. A hybrid optimization strategy is adopted,consisting of three optimization sub-strategies: stochastic optimization, deterministic optimiza-tion and local enumeration optimization, to dynamically reconstruct the problem structure. Thus,“transition” can be made from a local minimum point to reach other parts of the search space,traverse the whole search space, and obtain the global (approximate) optimal routing solution.Since any arbitrary initial routing solution can be used as the start point of the search, the initial-ization in SSTT algorithm is greatly simplified. SSTT algorithm has been tested on both MCNC benchmark circuits and industrial circuits, and the experimental results were compared with those of typical existing algorithms. The experimental results show that SSTT algorithm can obtain the global (approximate) optimal routing solution easily and quickly. Moreover, it can meet the needs of practical applications. The SSTT global routing algorithm gives a general-purpose routing solution.     

Deterministic VLSI block placement algorithm using Less Flexibility First principle

In this paper,a simple while effective deterministic algorithm for solving the VLSI block placement problem is proposed considering the packing area and interconnect wiring simultaneously.The algorithm is based on a principle inspired by observations of ancient professionals in solving their similar problems.Using the so-called Less Flexibility First principle,it is tried to pack blocks with the least packing flexibility on its shape and interconnect requirement to the empty space with the least packing flexibility in a greedy manner.Experimental results demonstrate that the algorithm,though simple,is quite effective in solving the problem.The same philosophy could also be used in designing efficient heuristics for other hard problems,such as placement with preplaced modules,placement with L/T shape modules,etc.     

FaSa: A fast and stable quadratic placement algorithm

Placement is a critical step in VLSI design because it dominates overall speed and quality of design flow.In this paper,a new fast and stable placement algorithm called FaSa is proposed.It uses quadratic programming model and Lagrange multiplier method to solve placement problems.And an incremental LU factorization method is used to solve equations for speeding up.The experimental results show that FaSa is very stable,much faster than previous algorithms and its total wire length is comparable with other algorithms.     

考虑光学邻近效应的详细布线算法

提出了一种考虑光学邻近效应的详细布线算法.该算法在布线过程中,充分考虑了线网走线相对位置及布线线形对其光学邻近效应的影响,通过相应的光刻模拟模型定义了用于估计光学邻近效应(optical proximity effect,OPE)的OPE费用函数,并采用OPE费用阈值控制Steiner树的生长方向和走线路径的选择,同时兼顾线网长度.为提高算法效率,避免布线过程中反复调用光学模拟程序带来的算法运行速度慢的问题,对可能的走线模式建立了计算OPE费用所需的光强查找表格,使算法的运行速度大大提高.在实际的工业用例上的实验结果表明,本文所提出的详细布线算法使布线结果中的OPE问题得到很大程度的改善,有利于后处理过程中的光学邻近效应校正技术的运用,算法的运行时间是可以接受的.     

一种新的无网格拆线重布算法

结合无网格布线的特点,提出一种新的无网格拆线重布算法.该算法显式地表示并动态更新线网所属区域的拥挤程度.在拆线重布进行待布线网的路径搜索时,每个扩展节点中增加拆除线网周边的拥挤权重,从而将待布线网的路径搜索过程和拆除线网的选择过程统一起来,有效地提高了被拆除线网重新布通的可能性.该算法利用改进的二叉区间树有效组织中间数据,降低计算的复杂度.实验结果表明,该算法能有效消除布线顺序对布线结果的影响,提高布通率,且算法运行速度较快.     

一个快速高效进行布线拥挤优化的总体布线器

设计实现了一个高效的线长模式下基于多处理机的并行总体布线器.通过对非时延驱动模式下串、并行算法的总运行时间和求解时间的比较,表明该并行算法能够在保证求解质量无明显变化的前提下大大加快总体布线算法的求解速度.同时,也提出了基于分布式体系结构的并行总体布线算法.     

一种新的无网格拆线重布算法

结合无网格布线的特点,提出一种新的无网格拆线重布算法.该算法显式地表示并动态更新线网所属区域的拥挤程度.在拆线重布进行待布线网的路径搜索时,每个扩展节点中增加拆除线网周边的拥挤权重,从而将待布线网的路径搜索过程和拆除线网的选择过程统一起来,有效地提高了被拆除线网重新布通的可能性.该算法利用改进的二叉区间树有效组织中间数据,降低计算的复杂度.实验结果表明,该算法能有效消除布线顺序对布线结果的影响,提高布通率,且算法运行速度较快.     

三维互连全耦合电容矩阵的层次式提取算法

基于直接边界元素法,提出一种边界电容矩阵概念,从而实现了三维互连电容的层次式提取算法.该算法将三维求解区域划分为若干小块,对每个小块分别计算其边界电容矩阵,再通过层次式合并算法便可得到全耦合互连电容矩阵.数值实验表明,本方法进行电容提取的速度比商业软件SpiceLink、虚拟多介质快速算法、区域分解法等均快一个数量级以上.     

SOC中Data-Path布图设计面临的挑战

目前所设计的系统级芯片(SOC)包含有多个data-path模块,这使得data-path成为整个G大规模集成电路(GSI)设计中最关键的部分.以往的布图理论及算法在许多方面已不能满足data-path布图设计的需要,这主要是由于传统的布图工具没有考虑data-path所特有的电路结构特点.Data-path具有规整的位片结构,具有很高的性能指标要求,如对于时延、耦合效应和串扰等性能都有严格的要求.此外,data-path中还存在大量成束状结构的BUS线网.文中提出了data-path布图设计所面临的挑战.从介绍data-path布图的基本问题入手,重点分析了data-path布图设计中的关键技术,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想.