Formation mechanism of bainitic ferrite and carbide

Superledges on the broad faces of bainitic ferrite plates have been observed with transmission electron microscope (TEM). The observed superledges, ranging from less than 1 to 24 nm in height, are imaged in three dimension by way of tilt operation under TEM. Also, an array of smaller superledges are observed to pile up in front of a secondary phase. Pileup of superledges in front of a barrier is indicative of the mobility of an individual superledge. The precipitation of carbide associated with bainitic ferrite is also studied. It is observed that a carbide of a wedgelike shape may exist in front of a superledge with its tip(i.e., thinner end) penetrating the austenite and its root (the other end) originating at α:γ boundary. This condition indicates that the observed carbides may nucleate at the austenite side of α:γ phase boundary and grow toward austenite matrix. This article is based on a presentation made at the Pacific Rim Conference on the “Roles of Shear and Diffusion in the Formation of Plate-Shaped Transformation Products,” held December 18-22, 1992, in Kona, Hawaii, under the auspices of ASM INTERNATIONAL’S Phase Transformations Committee.     

7.5 Gb/s monolithically integrated clock recovery circuit using PLLand 0.3-μm gate length quantum well HEMT's

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V     

New efficient designs for XOR and XNOR functions on the transistorlevel

Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

Damage and strain in pseudomorphic vs relaxed GexSi1−x layers on Si(100) generated by Si ion irradiation

We compare both the strain and damage that 100 keV Si irradiation at room temperature introduces in pseudomorphic and relaxed Ge_xSi_1−x films grown on Si(100) substrates. The ion range is such that the Si/Ge_xSi_1−x interface is not significantly damaged. The amount of damage produced in pseudomorphic and relaxed Ge_xSi_1−x layers of similar x for irradiation doses up to 2.5 × 10¹⁴ Si/cm² is the same, which proves that a pre-existing uniform strain does not noticeably affect the irradiation-induced damage. However, the irradiation-induced strain does depend on the pre-existing strain of the samples. Possible interpretations are discussed. On leave from Inst. voor Kern en Stralingsfysika, Catholic University of Leuven, Belgium.     

Dependence of critical current density on microstructure and processing of high-Tc superconductors

Microstructural origins for reduced weak-link behavior in high-J_c melt-processed YBCO, spray pyrolyzed thick films of Tl-1223, metallic precursor Y-124 polycrystalline powder-in-tube (PIT) wires and PIT Bi-2212/2223 are discussed. Since the materials studied are the highest J_c, polycrystalline, high-T_c superconductors fabricated worldwide, the results provide important guidelines for further improvements in superconducting properties, thereby enabling practical applications of these materials. It is found that strongly linked current flow within domains of melt-processed 123 occurs effectively through a single crystal path. In c-axis oriented, polycrystalline Tl-1223 thick films, local in-plane texture has been found to play a crucial role in the reduced weak-link behavior. Formation of “colonies” of grains with a common c-axis and modest in-plane misorientation was observed. Furthermore, a colony boundary in general has a varying misorientation along the boundary. Large regions comprised primarily of low angle boundaries were observed. Percolative transport through a network of such small angle boundaries appears to provide the nonweak-linked current path. Although powder-in-tube BSCCO 2212 and 2223 also appear to have a “colony” microstructure, there are some important differences. Colonies in BSCCO consist of stacks of grains with similar c-axis orientation in contrast to colonies in Tl-1223 films where few grains are stacked on top of one another. Furthermore, most grains within a colony in BSCCO have the same lateral dimensions as that of the colony, resulting largely largely in “twist” boundaries. Further microstructural characterization of high-J_c PIT 2212 and 2223 is currently underway. In the case of Y-124 wires, weak macroscopic in-plane texture is found. Additional measurements are underway to determine if a sharper, local in-plane texture also exists. It is found that in three of the four types of superconductors studied, reduced weak-link behavior can be ascribed to some degree of biaxial alignment between grains, either on a “local” or a “global” scale.     

Error monitoring issues for common channel signaling

Motivated by field data which showed a large number of link changeovers and incidences of link oscillations between in-service and out-of-service states in common channel signalling (CCS) networks, a number of analyses of the link error monitoring procedures in the SS7 protocol were performed by the authors. This paper summarizes the results obtained thus far and include the following: (a) results of an exact analysis of the performance of the error monitoring procedures under both random and bursty errors; (b) a demonstration that there exists a range of error rates within which the error monitoring procedures of SS7 may induce frequent changeovers and changebacks; (c) an analysis of the performance of the SS7 level-2 transmission protocol to determine the tolerable error rates within which the delay requirements can be met; (d) a demonstration that the tolerable error rate depends strongly on various link and traffic characteristics, thereby implying that a single set of error monitor parameters will not work well in all situations; and (e) some recommendations on a customizable/adaptable scheme of error monitoring with a discussion on their implementability. These issues may be particularly relevant in the presence of anticipated increases in SS7 traffic due to widespread deployment of advanced intelligent network (AIN) and personal communications service (PCS) as well as for developing procedures for high-speed SS7 links currently under consideration by standards bodies     

P-N double quantum well resonant interband tunneling diode withpeak-to-valley current ratio of 144 at room temperature

The current-voltage characteristics of the P-N double quantum well resonant interband tunneling (RIT) diodes in InAlAs-InGaAs system have been improved in this letter. The peak-to-valley current ratio (PVCR) is as high as 144 at room temperature. As we know, this is the highest room temperature PVCR ever reported in any tunneling devices. Moreover, the influence of the central barrier thickness varying from 10 Å to 30 Å on the device characteristics is also studied     

An approximate method for computing performance-related reliability of gracefully degrading systems

Using existing methods, the computation of performance-related reliability (PRR) of large-scale gracefully degrading systems is very tedious and time consuming. In this paper, the behaviour of such systems is respectively modeled as two types of diffusion processes according to their reconfiguration coverage. If the coverage is 1 (i.e. the reconfiguration is always successful), it is modeled as a regular diffusion. If, on the other hand, the coverage is less than one, it is modeled as diffusion with killing. Kolmogorov backward equations for regular diffusion processes and for diffusions with killing are then applied to compute the PRR. The methods have been applied in several examples, and the results satisfactorily agree with the accurate results.