High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is implemented by the creation of a voltage drop using embedded circuit elements. The final clamp voltage is tuned to exceed the power supply level, thus eliminating the potential for latchup. The design is validated by ESD pulse measurements performed on test structures with cascoded, triggered LVTSCRs for 5.5-V tolerant I/O pins in an 0.18-/spl mu/m CMOS process. The results of the first part of the study were used to propose another design for the LVTSCR with a high holding voltage based on emitter area reduction. The proposed device is validated using three-dimensional simulations and experimental analysis.     

Organic light-emitting devices with multi-shell quantum dots connected with polythiophene derivatives

The results of an experimental study of organic light-emitting diodes with poly-2,5-(3,4-diamino thieno[2,3-b]thiophene)-4,4’-amidoarylene transport layers and CdSe/CdS/ZnS quantum dots, the CdSe core of which has an average diameter of 4.1 nm, are presented. A suggestion is made regarding the possible conjugation of quantum dots and polythiophenes, which would substantially improve the characteristics of the light-emitting diodes in the case of optimization of their structure.     

Selection of rational surface configuration For roller press tires

Powder Metallurgy and Metal Ceramics - Roller presses are most common pelletizing and compacting machines for fine-grained materials in metallurgy and related industries. Rollers with replaceable...     

Quasi-3D simulation approach for comparative evaluation of triggering ESD protection structures

A 2D simulation approach that takes into account the 3D effects of electro-thermal instability during electrostatic discharge (ESD) operation, is presented. The method is used to provide physical evaluation of a safe operation regime for BiCMOS ESD protection structures and circuits. The methodology is demonstrated through the application to Si–Ge NPN bipolar transistors, snapback NMOS and LVTSCR structures.