Formulation of a ceramic ink for a wide-array drop-on-demand ink-jet printer

This paper describes the methodology for simulating a reprographic ink with a ceramic ink based on a commercially available zirconia powder for direct ceramic ink-jet printing. Of over-riding importance was matching viscosity and this was tested systematically by using a mineral oil–hexane binary system. Of secondary importance was adjustment of the pressure defect behind the nozzle to compensate for small differences in surface tension. The inks tested in the wide array print-head were based on low electrical conductivity liquids to avoid damage to the electroding system. The organic binder for the zirconia ink was paraffin wax and the dispersant was a hydroxystearic acid based polyester.     

Practical OSPF traffic engineering

Open Shortest Path First (OSPF) traffic engineering (TE) is intended to bring long-awaited traffic management capabilities into IP networks, which still rely on today's prevailing routing protocols: OSPF or IS-IS. In OSPF, traffic is forwarded along, and split equally between, equal cost shortest paths. In this letter, we formulate the basic requirements placed on a practical TE architecture built on top of OSPF and present a theoretical framework meeting these requirements of practicality. The main contribution of our work comes from the recognition that coupled with an instance of the maximum throughput problem there exists a related inverse shortest-path problem yielding optimal OSPF link weights.     

Techniques for high-frequency integrated test and measurement

This paper describes techniques for the on-chip measurement of high-frequency and/or high-bandwidth electrical phenomena in ultra large-scale integration environments. The techniques rely on the integration of multiple compact and robust electronic test devices, or cores, at various locations within an integrated circuit. The cores consist primarily of signal generators that approximate the output of a sigma-delta modulator using finite repetitious bit patterns and a small set of highly robust analog components. They are capable of digitizing on-chip signals at gigahertz rates even using low-cost manufacturing processes. Simple communication between the multiple cores enables the migration of many "board-level" type measurements down to the chip level.     

PNNI-based control plane for automatically switched optical networks

Much effort has been spent on the definition of control plane protocols for automatically switched optical networks (ASON). Most of the proposals brought into the standardization for an International Telecommunications Union-Telecommunication Sector, Internet Engineering Task Force, and Optical Internetworking Forum are based on Internet protocol concepts. One such proposal is the generalized multi-protocol label switching (GMPLS), an extension of the MPLS traffic engineering control plane model that includes nonpacket switched technologies (time, wavelength, and fiber switching). Recently, the potential use of private network-network interface (PNNI) in ASONs has been discussed as an alternative proposal by the standardization bodies. The goal of this paper is to appropriately adapt asynchronous transfer mode into an optical PNNI (O-PNNI) protocol that can be used as the control plane of ASONs. The paper also provides a critical viewpoint on the potential usage of either O-PNNI or GMPLS control plane and analyzes the pros and cons of each. The methodology adopted toward devising O-PNNI hinges on reviewing PNNI along with ASON recommendations in order to determine the set of PNNI features that require adaptation. Having identified these features we engineer and present appropriate solutions relating to routing, signaling and addressing aspects.     

A fuzzy logic based-method for prognostic decision making in breast and prostate cancers

Accurate and reliable decision making in oncological prognosis can help in the planning of suitable surgery and therapy, and generally, improve patient management through the different stages of the disease. In recent years, several prognostic markers have been used as indicators of disease progression in oncology. However, the rapid increase in the discovery of novel prognostic markers resulting from the development in medical technology, has dictated the need for developing reliable methods for extracting clinically significant markers where complex and nonlinear interactions between these markers naturally exist. The aim of this paper is to investigate the fuzzy k-nearest neighbor (FK-NN) classifier as a fuzzy logic method that provides a certainty degree for prognostic decision and assessment of the markers, and to compare it with: 1) logistic regression as a statistical method and 2) multilayer feedforward backpropagation neural networks an artificial neural-network tool, the latter two techniques having been widely used for oncological prognosis. In order to achieve this aim, breast and prostate cancer data sets are considered as benchmarks for this analysis. The overall results obtained indicate that the FK-NN-based method yields the highest predictive accuracy, and that it has produced a more reliable prognostic marker model than both the statistical and artificial neural-network-based methods.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported