Integrating design and measurement

At the 2004 International Instrumentation and Measurement Conference in Italy, a number of us were discussing the growing importance of system-level design and the implications for simulation and measurement technologies. It was puzzling to us that technology continues to increase in complexity, yet the last two decades have seen the design world of simulation and modeling diverge from the world of measurement and testing. Today's systems, whether they are commercial products or scientific experiments, require a convergence of technologies that makes performance measurement and validation not only more critical but also more prone to error. In the discussions a point that came up repeatedly was the value of bringing the design and test communities closer together, and it was suggested that it was timely to highlight this issue. With that in mind, this note aims to stimulate community discussion by first examining some benefits and challenges of integration and then outlining possible directions for collaboration between the simulation and measurement communities.     

Optimal tradeoffs for location-based routing in large-scale ad hoc networks

Existing location-based routing protocols are not versatile enough for a large-scale ad hoc environment to simultaneously meet all of the requirements of scalability, bandwidth efficiency, energy efficiency, and quality-of-service routing. To remedy this deficiency, we propose an optimal tradeoff approach that: 1) constructs a hybrid routing protocol by combining well-known location-update schemes (i.e., proactive location updates within nodes' local regions and a distributed location service), and 2) derives its optimal configuration, in terms of location-update thresholds (both distance and time-based), to minimize the overall routing overhead. We also build a route-discovery scheme based on an Internet-like architecture, i.e., first querying the location of a destination, then applying a series of local-region routing until finding a complete route by aggregating the thus-found partial routes. To find the optimal thresholds for the hybrid protocol, we derive the costs associated with both location updates and route discovery as a function of location-update thresholds, assuming a random mobility model and a general distribution for route request arrivals. The problem of minimizing the total cost is then cast into a distributed optimization problem. We first prove that the total cost is a convex function of the thresholds, and then derive the optimal thresholds. Finally, we show, via simulation, that our analysis results indeed capture the real behavior.     

Analysis of multiple FSS screens of unequal periodicity using an efficient cascading technique

In this paper, we present an efficient cascading procedure for analyzing frequency selective surface (FSS) systems consisting of multiple FSS screens of unequal periodicity embedded in multiple dielectric layers. In this procedure, we first find a global period for the FSS system by studying the composite in its entirety. Next, we compute the scattering matrix [S] of each of the FSS subsystems for the global Floquet harmonics by applying a relationship we establish that maps the [S] matrix of the subsystem for the individual Floquet harmonics to that for the global harmonics. This mapping-cum-filling process substantially reduces the effort needed to compute the [S] matrix of a subsystem. Finally, we compute the [S] of the entire system by applying a modified cascading formulation, in which one matrix inversion step is eliminated, resulting in a reduction in the total computing resource requirement as well as time. Two numerical examples are given to illustrate the efficiency and effectiveness of the technique.     

Minimizing power dissipation in optical interconnects at low voltage using optimal modulator design

A strong motivation for insertion of optical interconnects in short-distance applications such as chip-to-chip or back-plane communication, apart from high bit rates, is their potential to achieve these bit rates at low power compared to the currently prevalent copper based interconnects. Thus, it is imperative to construct design methodologies which minimize the total optical link power dissipation. We present one such methodology, where we optimize the quantum-well modulators to minimize the power dissipation in modulator-based optical interconnects. In the first part of the paper, the focus is on obtaining the optimal modulator metrics [contrast ration (CR) and insertion loss], which yield the lowest total power (receiver and the modulator). The trends are studied as a function of the input laser power and bit rate. Having obtained the desirable modulator metrics and the corresponding power dissipation, in the second part, the focus is on the feasibility of these metrics in the light of voltage swing constraints. The biggest concern with the modulator based optical link is the low CR, especially at low voltage swing. While studying these concerns, we also provide insight into the physical design of the modulator including, its intrinsic region thickness, pre-bias voltage, and the size and the number of quantum-wells. Specifically, we outline the method to obtain the design parameters, which allows minimum power dissipation with the least laser power. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.     

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

An on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed. This SRAM supports three operating modes - high-speed active mode, low-leakage low-speed active mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme. The combination of three operating modes and the SPC scheme realizes low-power operation under actual usage conditions. It operates at 300 MHz, with leakage of 25 /spl mu/A/Mb in standby mode, and 50 /spl mu/A/Mb at the low-leakage active mode. This SRAM also uses a self-bias write scheme that decreases of minimum operating voltage by about 100 mV.     

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.     

Coding approaches to fault tolerance in linear dynamic systems

This paper discusses fault tolerance in discrete-time dynamic systems, such as finite-state controllers or computer simulations, with focus on the use of coding techniques to efficiently provide fault tolerance to linear finite-state machines (LFSMs). Unlike traditional fault tolerance schemes, which rely heavily-particularly for dynamic systems operating over extended time horizons-on the assumption that the error-correcting mechanism is fault free, we are interested in the case when all components of the implementation are fault prone. The paper starts with a paradigmatic fault tolerance scheme that systematically adds redundancy into a discrete-time dynamic system in a way that achieves tolerance to transient faults in both the state transition and the error-correcting mechanisms. By combining this methodology with low-complexity error-correcting coding, we then obtain an efficient way of providing fault tolerance to k identical unreliable LFSMs that operate in parallel on distinct input sequences. The overall construction requires only a constant amount of redundant hardware per machine (but sufficiently large k) to achieve an arbitrarily small probability of overall failure for any prespecified (finite) time interval, leading in this way to a lower bound on the computational capacity of unreliable LFSMs.     

Outage capacities and optimal power allocation for fading multiple-access channels

We derive the outage capacity region of an M-user fading multiple-access channel (MAC) under the assumption that both the transmitters and the receiver have perfect channel side information (CSI). The outage capacity region is implicitly obtained by deriving the outage probability region for a given rate vector. Given a required rate and average power constraint for each user, we find a successive decoding strategy and a power allocation policy that achieves points on the boundary of the outage probability region. We discuss the scenario where an outage must be declared simultaneously for all users (common outage) and when outages can be declared individually (individual outage) for each user.     

Self-Adapting Linear Algebra Algorithms and Software

One of the main obstacles to the efficient solution of scientific problems is the problem of tuning software, both to the available architecture and to the user problem at hand. We describe approaches for obtaining tuned high-performance kernels and for automatically choosing suitable algorithms. Specifically, we describe the generation of dense and sparse Basic Linear Algebra Subprograms (BLAS) kernels, and the selection of linear solver algorithms. However, the ideas presented here extend beyond these areas, which can be considered proof of concept.