The Search for Alternative Computational Paradigms

Nanometer processes are characterized by extremes of process variations, noise, soft errors, and other nonidealities, which threaten to nullify the intrinsic benefits of scaling. The resulting robustness and energy efficiency problem cannot be addressed in a cost-effective manner solely through advances in manufacturing. Alternative models of computation are needed that thrive in the presence of statistical variations in the underlying device and circuit fabric. This article explores communications-inspired models of computation supported by innovative robust circuit and logic fabric design approaches. These models share the common feature of leveraging dense networks with information exchange and coupling among nodes to enhance robustness without compromising energy efficiency. Promising post-silicon devices such as carbon nanotubes (CNTs) offer an attractive platform on which to build such computational systems. This article identifies opportunities and challenges in designing robust and low-power SoCs in emerging nanoscale process technologies, employing radically new modes of computation.     

Ozone and Oxygen permeation behavior of silicone capillary membranes employed in membrane ozonators

The permeabilities and selectivities of O₃, O₂, and N₂ through silicone capillary membranes employed to degrade organic pollutants in water or air have been experimentally determined. These characteristics have been studied for silicone membranes used in membrane reactors having the following conditions: O₃ in O₂ on one side of the membrane, and either water containing pollutants or a perfluorocarbon (FC) phase containing pollutants on the other side. The permeability of O₃ (8.8 e-13 kgmol · m/m² · s · kPa) is four times that of O₂ through virgin silicone rubber. Exposure to O₃ modifies the polymer and alters the permeabilities of O₃ and O₂. The presence of water with O₃ leads to an increase in O₃ and O₂ permeability (∼ 30%) and an increase in the selectivity, (∼ 10%). The increased permeabilities are likely to be due to the formation of peroxides on the surface and possibly in the polymer. When the silicone capillary membranes were exposed to a perfluorocarbon (FC), the permeabilities of O₃ and O₂ decreased (∼ 9%) due to an increase in crosslinking in the polymer matrix; there was also a slight increase in (∼ 2%), which can be ascribed to the smaller molecular sieving radius of O₂ compared to N₂. © 1998 John Wiley & Sons, Inc. J Appl Polym Sci 69: 1263–1273, 1998     

A coding framework for low-power address and data busses

This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f₁. Next, a variant of entropy coding function f₂ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f₁ and f₂ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 μm CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes     

Synthesis and characterization of polymeric ionic liquid poly(imidazolium chloride-1,3-diylbutane-1,4-diyl)

Polymeric ionic liquid poly(imidazolium chloride-1,3-diylbutane-1,4-diyl) with imidazolium cation groups built into the main chain was prepared using two different routes in 92–95% yield, and characterized by FT-IR, ¹H, ¹³C NMR, TGA, and elemental analysis. The first method involved the heating of neat 1-(4-chlorobutyl)-1H-imidazole, whereas the second method involved the heating of an equimolar mixture of 1,1′-(1,4-butanediyl)-bis-imidazole and 1,4-dichlorobutane.     

Energy-efficient soft error-tolerant digital signal processing

In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs low-complexity estimators of a main DSP block to achieve reliable operation in the presence of soft errors. Three distinct ASET techniques - spatial, temporal and spatio-temporal- are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that the proposed techniques provide robustness in the presence of soft error rates of up to P/sub er/=10/sup -2/ and P/sub er/=10/sup -3/ in a single-event upset scenario. The power dissipation of the proposed techniques ranges from 1.1 X to 1.7 X (spatial ASET) and 1.05 X to 1.17 X (spatio-temporal and temporal ASET) when the desired signal-to-noise ratio SNR/sub des/=25 dB. In comparison, the power dissipation of the commonly employed triple modular redundancy technique is 2.9 X.     

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements     

Coding for system-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.     

Reliable low-power digital signal processing via reduced precision redundancy

In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage V/sub dd-crit/) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.     

A pipelined adaptive lattice filter architecture

The stochastic gradient adaptive lattice filter is pipelined by the application of relaxed look-ahead. This form of look-ahead maintains the functional behavior of the algorithm instead of the input-output mapping and is suitable for pipelining adaptive filters. The sum and product relaxations are employed to pipeline the filter. The hardware complexity of the pipelined filters is the same as for the sequential filter and is independent of the level of pipelining or speedup. Two pipelined architectures along with their convergence analyses are presented to illustrate the tradeoff offered by relaxed look-ahead. Simulation results supporting the conclusions of the convergence analysis are provided. The proposed architectures are then employed to develop a pipelined adaptive differential pulse-code modulation (DPCM) codec for video compression applications. Speedup factors up to 20 are demonstrated via simulations with image data