VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN andbroadband access

We present: (1) system design issues for the implementation of 51.84 Mb/s ATM-LAN and broadband access transceivers and (2) a pipelined fractionally spaced linear equalizer (FSLE) architecture. Signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints are addressed. For the LAN environment, major channel impairments include near-end crosstalk (NEXT), intersymbol interference (ISI), and impulse noise. The broadband access environment suffers from far end crosstalk (FEXT), ISI, radio-frequency interference (RFI), impulse noise, and splitter losses. Measured characteristics of the channel are compared with analytical models. These are employed in the design of the transmitter/receiver algorithms. The carrierless amplitude/phase (CAP) transmission scheme is presented as a practical bandwidth-efficient scheme for these applications. An adaptive FSLE employed in a CAP receiver eliminates ISI, suppresses NEXT (for ATM-LAN) and FEXT (for broadband access), and provides robustness to timing jitter. However, fractional tap spacing in combination with the high-data rates results in a high sample rate adaptive computation. Fortunately, throughput enhancing methods such as pipelining can be used for high-speed/low-power operation. A hardware-efficient pipelined architecture for the adaptive FSLE equalizer is presented. This has been developed using relaxed look-ahead, which maintains the algorithm functionality rather than the input-output mapping. Simulation and experimental results for high-speed digital CAP transceivers for LAN and broadband access are also presented     

Improved estimates via exponential sums for the minimum distance ofZ4-linear trace codes

An upper hound for Weil-type exponential sums over Galois rings was derived by Kumar, Helleseth, and Calderbank (see ibid., vol.41, no.3, p.456, 1995). This bound leads directly to an estimate for the minimum distance of Z₄-linear trace codes. An improved minimum-distance estimate is presented. First, McEliece's result on the divisibility of the weights of binary cyclic codes is extended to Z₄ trace codes. The divisibility result is then combined with the techniques of Serre (1983) and of Moreno and Moreno (see ibid., vol.40, no.11, p.1101, 1994) to derive the improved minimum-distance estimate. The improved estimate is tight for the Kerdock code as well as for the Delsarte-Goethals codes     

Cell distribution profiles in three-dimensional scaffolds with inverted-colloidal-crystal geometry: modeling and experimental investigations

Limited ingrowth of stromal cells is observed when a three-dimensionally ordered scaffold possessing inverted-colloidal-crystal geometry is used to culture adherent cells. In this work, a computational model explaining, as well as predicting, experimental cell distributions is developed. It incorporates a modified Contois cell-growth model that includes the effects of nutrient saturation, competitive product inhibition, and cell-contact inhibition to describe the scaffold-cell system. Our results agree with the hypothesis that the rapid growth of cells on the surface of the scaffold depletes the nutrient supply to the core, resulting in the preferential growth on the exterior of the scaffold. When the cells are cultured in a scaffold subjected to a uniform velocity field, they penetrate to a greater extent into the scaffold core. Alternative seeding and culture strategies are suggested and evaluated.     

Inhibition Effects of Chloroquinolines on Corrosion of Mild Steel in Hydrochloric Acid Solution

The corrosion inhibition efficiencies of four compounds namely N-[(1E)-(2-chloroquinolin-3-yl)methylene]-N-phenylamine(CQMA),N-(1E)-(2-chloroquinolin-3-yl)methylene]-N-(4-fluorophenyl)amine(CQMFA),N-(4-chloro phenyl)-N-[(1E)-(2-chloroquinolin-3-yl)methylene]amine(CQMCA),and N-(4-bromo phenyl)-N-[(1E)-(2-chloroquinolin-3-yl)methylene]amine(CQMBA)on mild steel corrosion in hydrochloric acid media were investigated using mass loss,potentiodynamic polarization and electrochemical impedance spectroscopy.For all the studied inhibitors the inhibition efficiency values were found to increase with increasing concentration up to 5.00×10-4 mol·dm-3.Scanning electron microscopic technique showed the formation of a thick film on the steel surface in the presence of inhibitors.     

Joint Equalization and Coding for On-Chip Bus Communication

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.     

Energy Efficient VLSI Architecture for Linear Turbo Equalizer

In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30–60% and 10–60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.     

Toward achieving energy efficiency in presence of deep submicronnoise

Presented in this paper are: 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed f_c and supply voltage V_dd; b) transition activity t in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) energy dissipation are derived. A surprising result is that in a scenario where dynamic component of power dissipation dominates, the supply voltage for minimum energy operation (V_{dd, opt}) is greater than the minimum supply voltage (V_{dd, min})for reliable operation. We then propose noise tolerance via coding to approach the lower bounds on energy dissipation. We show that the lower bounds on energy for an off-chip I/O signaling example are a factor of 24× below present day systems. A very simple Hamming code can reduce the energy consumption by a factor of 3×, while Reed-Muller (RM) codes give a 4× reduction in energy dissipation     

Dynamic algorithm transforms for low-power reconfigurable adaptiveequalizers

In this paper, we present low-power reconfigurable adaptive equalizers derived via dynamic algorithm transforms (DATs). The principle behind DAT is that conventional signal processing systems are designed for the worst case and are not energy-optimum on average. Therefore, significant energy savings can be achieved by optimally reconfiguring the hardware in these situations. Practical reconfiguration strategies for adaptive filters are presented. These strategies are derived as a solution to an optimization problem. The optimization problem has energy as the objective function and a constraint on the algorithm performance (specifically the SNR). The DAT-based adaptive filter is employed as an equalizer for a 51.84 Mb/s very high speed digital subscriber loop (VDSL) over 24-pair BKMA cable. The channel nonstationarities are due to variations in cable length and number of far end crosstalk (FEXT) interferers. For this application, the traditional design is based on 1 kft cable length and 11 FEXT interferers. It was found that up to 81% energy savings can be achieved when cable length varies from 1-0.1 kft and the number of FEXT interferers varies from 11 to 4. On the average, 53% energy savings are achieved as compared with the conventional worst-case design     

Low-power MIMO signal processing

In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.     

VLSI architectures for SISO-APP decoders

Very large scale integration (VLSI) design methodology and implementation complexities of high-speed, low-power soft-input soft-output (SISO) a posteriori probability (APP) decoders are considered. These decoders are used in iterative algorithms based on turbo codes and related concatenated codes and have shown significant advantage in error correction capability compared to conventional maximum likelihood decoders. This advantage, however, comes at the expense of increased computational complexity, decoding delay, and substantial memory overhead, all of which hinge primarily on the well-known recursion bottleneck of the SISO-APP algorithm. This paper provides a rigorous analysis of the requirements for computational hardware and memory at the architectural level based on a tile-graph approach that models the resource-time scheduling of the recursions of the algorithm. The problem of constructing the decoder architecture and optimizing it for high speed and low power is formulated in terms of the individual recursion patterns which together form a tile graph according to a tiling scheme. Using the tile-graph approach, optimized architectures are derived for the various forms of the sliding-window and parallel-window algorithms known in the literature. A proposed tiling scheme of the recursion patterns, called hybrid tiling, is shown to be particularly effective in reducing memory overhead of high-speed SISO-APP architectures. Simulations demonstrate that the proposed approach achieves savings in area and power in the range of 4.2%-53.1% over state of the art.