A loss aware scalable topology for photonic on chip interconnection networks

The demand for robust computation systems has led to the increment of the number of processing cores in current chips. As the number of processing cores increases, current electrical communication means can introduce serious challenges in system performance due to the restrictions in power consumption and communication bandwidth. Contemporary progresses in silicon nano-photonic technology have provided a suitable platform for constructing photonic communication links as an alternative for overcoming such problems. Topology is one of the most significant characteristics of photonic interconnection networks. In this paper, we have introduced a novel topology, aiming to reduce insertion loss in photonic networks; detailed analysis of the proposed topology has also been provided based on synthetic and real application benchmarks using a cycle-accurate simulation environment. Results demonstrate that the proposed topology outperforms other considered topologies in terms of physical-layer parameters, such as insertion loss, and provides better scalability. Moreover, such improvement in physical-layer parameters has caused system performance parameters to improve significantly. For instance, the topology yields an improvement of at least 406 % in bandwidth, compared to the best case, when leveraging synthetic traffic patterns. Furthermore, when using scientific applications, execution time and energy efficiency are improved up to 85 % and 97 %, respectively.     

A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) in which irregular Mesh-based and fault tolerant NoCs that are using Table-based routing. The proposed approach encompasses TPG and TRA located in the Network Adapter (NA) as well as a Packet Comparing Module (PCM) embedded in the routers. The approach, in addition, with a high scalability leads to 100% Test Coverage (TC) and 82.3% capability of diagnosing faulty channels in NoCs with a high scale. Furthermore, the approach is capable of being performed within one Round (two phase) run with a total time of 70 clocks which is considered as cost-effective compared with the preceding methods. The simulation results demonstrate that the hardware cost of PCM is trivial compared with the hardware of RASoC, HERMES, Æthereal and Vici routers.