A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

An algorithm is presented for obtaining placements of cell-based very large scale integrated circuits, subject to timing constraints based on table-lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well-known quadratic placement with bottom-up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.     

局部K参数模拟方法的稳定性证明

采用文献(魏洪川,喻文健,杨柳,等.基于 K 参数思想的快速三维互连电感电阻提取算法.电子学报,2005,33(8):1365-1369)中提出的算法选取窗口,证明基于此方法提取的部分磁阻矩阵 K 正定,进而证明基于该矩阵的模拟稳定.     

双金属层门阵列跨单元行布线问题与算法

在双金属层门阵列布图中,跨单元行的走线可以直接在单元上进行,这些单元被称为“走线块”.充分地利用走线块上的两层走线空间,可以降低通道密度并减少通孔数.本文给出走线块布线问题及求解算法。包括三个过程:首先确定走线块引线端的相对位置关系,其次是定位引线端,最后实现走线块内的连接.给出的算法已经用C语言实现并嵌入一门阵布图系统.实例运行结果表明提出的算法可以有效地降低通道密度和提高通道布通率.