MPEG-4中的无限制运动补偿的实现

在MPEG-4的简单级编解码中,针对摄像头的平移或旋转,在帧间编码模式下,对参考帧需要进行数据的外扩.本文是在Linux系统下,实现了一种以宏块为单位的数据填充的无限制运动补偿技术,同时还提出了另外一种以字节为单位的数据填充的无限制运动补偿技术.     

嵌入式MPEG-4视频的流控算法

输出比特流的控制是影响MPEG-4视频编码器在低速率无线信道下传输的一个重要因素,控制的好坏将直接关系到解码图像的质量以及无线通道传输比特流的稳定性.充分理解TMS320C55x DSP芯片的结构和实时视频处理的特性,进行流控算法的研究,在基于OMAP的嵌入式多媒体开发平台上,模拟实际的无线信道,比较好的实现了流控技术.     

具有增益失配校正的I/Q双通道数模转换器设计

This paper presents a two-channel 12-bit current-steering digital-to-analog converter(DAC) for I and Q signal paths in a wireless transmitter.The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA.A gain matching circuit is proposed to reduce gain mismatch between the I and Q channels.The tuning range is±24%of full scale and the minimum resolution is 1/16 LSB.To further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch energy.The chip has been processed in a standard 0.13μm CMOS technology.Gain mismatch between a 1-channel DAC and a Q-channel DAC is measured to be approximately 0.13%.At 120-MSPS sample rate for 1 MHz sinusoidal signal,the spurious free dynamic range (SFDR) is 75 dB.The total power dissipation is 62 mW and has an active area of 1.08 mm2.     

基于TMS320DSC21的视频编码系统设计

介绍了TI公司推出的应用于视频、图像处理方面的DSP芯片——TMS320DSC21，该芯片具有低功耗和双核结构的特点。根据其软硬件特点提出了一种在DSC21开发板上实现H．263视频编码系统的结构。同时为了进一步提高编码速度，对此结构和运动估计算法等进行了优化处理，并最终在DSC21开发板上实现了此方案。通过对压缩率、峰值信噪比和功耗3个方面的评估表明：该系统设计具有简捷、高效、低功耗等优点。这种低功耗、完全可编程的DSP解决方案也使实时视频功能在成像因特网终端上的广泛应用成为可能。     

一种快速IrDA的设计与FPGA实现

简单介绍了IrDA协议以及在IrDA协议中数据传输的格式;根据快速IrDA的功能将其划分成若干模块,进行层次化设计,详细描述了在快速IrDA中的几个主要(关键)模块的实现方法;利用Verilog HDL实现了该设计,并利用Metor公司的Modelsim进行了仿真测试以及Synplicity公司的Synplify进行了综合来验证该设计的正确性。     

蓝牙实时视频传输系统设计与实现

文中设计了一种基于蓝牙技术的嵌入式视频传输系统。该系统采用了多种数据缓存机制使MPEG-4视频码流能适应蓝牙信道要求，实现了高质量实时视频的无线传输。实验测试表明，该系统在图像质量、时延上都达到了应用要求。     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.