应用于2Mb/s GMSK调制的CMOS低功耗全差分Sigma-Delta频率综合器

设计了应用于GMSK调制,工作在2.4GHz,CMOS全差分的∑-△频率综合器.调制器中采用预补偿的分数N锁相环.推导了Ⅱ型三阶锁相环的传输函数,并指出影响环路传输函数的重要参数.介绍了校准重要的环路参数的方法.锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵.设计的电路利用0.18μm 1P6M CMOS工艺进行仿真.由于锁相环的组成模块中采用了低功耗设计,锁相环的功耗仅为11mW左右,调制器的数据率达到2Mb/s.     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

一种38.4~43.4 GHz CMOS压控振荡器

设计了一种基于65 nm CMOS工艺的交叉耦合全差分40 GHz压控振荡器(VCO)。为了减小仿真结果与测试结果的差距,对电感及其连接其他元件而延长的金属线在电磁场仿真软件里重新进行了仿真。设计中应用了厚栅容抗管来增大电压的调谐范围,从而实现更高的频率覆盖范围。流片后的测试结果表明,VCO的振荡频率覆盖38.4~43.4 GHz,调谐范围达到12.2%,符合基于无线局域网IEEE 802.11ad标准设计的两级下变频60 GHz无线收发机对本振频率的要求。当振荡频率为39 GHz时,应用该VCO的锁相环锁定在41.76 GHz时测得1 MHz偏移频率处的相位噪声为－90.9 dBc/Hz。芯片采用1 V电源电压供电,功耗为5.7~8.6 mW,核心芯片面积为(0.197×0.436) mm²。     

集成低功耗CMOS压控振荡器及其二分频器

实现了应用于无线局域网收发机的集成低功耗CMOS压控振荡器及其二分频器.压控振荡器是由在片对称螺旋型电感和差分容抗管组成的LC负阻型振荡器,而二分频器采用了ILFD结构.由于采用了差分LC元件和ILFD技术,整个电路的功耗很低.该电路已经用0.18μm CMOS工艺实现.测试结果表明该电路能产生低相位噪声的3.6/1.8GHz双带本振信号,并具有很宽的可控频率范围.当电源电压为1.5V时,该电路消耗了5mA的电流.芯片面积为1.0mm×1.0mm.     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.     

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity(10Ω·cm) silicon substrate is presented.The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization.The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane.The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance.The simulated S11 is less than –10 dB over 46–95 GHz,which is well matched with the measured results over the available 40–67 GHz frequency range from our measurement equipment.A maximum gain of –5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansoft HFSS simulation.Compared with the current state-of-the-art devices,the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.     

用于2.4GHz无线局域网收发机的CMOS混频器

描述了采用CMOS工艺技术,用于2.4GHz无线局域网收发机的上变频器/下变频器的实现.由于采用class-AB类工作模式的输入级,该下变频器具有很高的线性度.同时,该输入级也完成了输入阻抗匹配和单端信号到差分信号的转换功能.它们采用0.18μm CMOS工艺实现.为了说明它们的性能,文中给出了每个模块的测试结果.     

CMOS功率放大器在射频识别技术中的应用概述

针对国内外射频识别技术的迅猛发展,结合射频识别技术的应用背景,阐述了读写器中最大的耗能器件—功率放大器的研究现状;指出CMOS工艺应用于功率放大器设计的局限性和可行性;最后,探讨了将CMOS功率放大器应用于射频识别技术的主要研究方向。     

2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.