The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metal- oxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H+ generated during NBTI stress.     

Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions

To enhance the reverse blocking capability with low specific on-resistance,a novel vertical metal-oxidesemiconductor field-effect transistor(MOSFET) with a Schottky-drian(SD) and SD-connected semisuperjunctions(SDD-semi-SJ),named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional(2D) numerical simulations.The SD contacted with the n-pillar exhibits the Schottky-contact property,and that with the p-pillar the Ohmic-contact property.Based on these features,the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions(SJ) or semisuperjunctions(semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage(BV) and the specific on-resistance(R_(on)A).For a given pillar width and n-drift thickness,there exists a proper range of n-drift concentration(N),in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of R_(on)A-BV compared to the predication of SJ MOSFET in the forward applications.And what is much valuable,in this proper range of N,the desired BV and good trade-off could be achieved only by determining the pillar thickness,with the top assist layer thickness unchanged.Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of R_(on)A-BV improvement in SD-D-semi-SJ MOSFET.These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.     

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability （NBTI） and stress-induced leakage current （SILC） both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts： the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

增强型AlGaN/GaN高电子迁移率晶体管高温退火研究

深入研究了两种增强型AlGaN/GaN高电子迁移率晶体管(HEMT)高温退火前后的直流特性变化.槽栅增强型AlGaN/GaN HEMT在500 ℃ N₂中退火5 min后,阈值电压由0.12 V正向移动到0.57 V,器件Schottky反向栅漏电流减小一个数量级.F注入增强型AlGaN/GaN HEMT在 400 ℃ N₂中退火2 min后,器件阈值电压由0.23 V负向移动到-0.69 V,栅泄漏电流明显增大.槽栅增强型器件退火过程中Schottky有效势垒     

茶碱分子印迹聚酰亚胺纳米纤维膜的制备与表征

以聚酰胺酸(PAA)溶液为原料,采用静电纺丝法制备了聚酰胺酸纳米纤维膜(PAAM),热处理脱水后获得聚酰亚胺纳米纤维膜(PIM)。采用PIM表面预涂覆聚甲基丙烯酸(PMAA),以茶碱(THO)为模板分子、偶氮二异丁腈(AIBN)为引发剂、乙二醇二甲基丙烯酸酯(EDMA)为交联剂、氯仿为溶剂,在PIM表面进行了热交联反应,制备了THO分子印迹聚酰亚胺纳米纤维复合膜(PIMIM)。讨论了纺膜条件,并用傅里叶红外光谱与扫描电镜分别表征了PIMIM的结构和形态,比较了THO的洗脱方式。结果表明:较佳的纺膜条件为纺丝电压15.0kV、接收距离12.0cm和纺丝液流量0.5mL/h。以PIM为支撑体,获得了聚酰亚胺纳米纤维间有分子印迹层的PIMIM。PIMIM对THO的静态吸附结合容量达144μmol/g,对THO与可可碱(TB)的选择性分离因子达1.96。对PIMIM循环再生,索氏提取法优于超声洗脱法。     

Study on the negative bias temperature instability effect under dynamic stress

This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress.Under alternant stress,the degradation smaller than that of single negative stress is obtained.The smaller degradation is resulted from the recovery of positive stress.There are two reasons for the recovery.One is the passivation of H dangling bonds,and another is the detrapping of charges trapped in the oxide.Under different frequencies of AC stress,the parameters all show regular degradation,and also smaller than that of the direct current stress.The higher the frequency is,the smaller the degradation becomes.As the negative stress time is too small under higher frequency,the deeper defects are hard to be filled in.Therefore,the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.     

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75--90\,nm), which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage ($V_{\rm d}$) stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different $V_{\rm d}$ stresses in order to understand the relations between peak of substrate current ($I_{\rm sub}$) and channel length/stress voltage.     

Fabrication and Characteristics of AIInN/A1N/GaN MOS-HEMTs with Ultra-Thin Atomic Layer Deposited Al2O3 Gate Dielectric

Al0.85In0.15N//AlN/GaN metal-oxide-semiconductor high electron mobility transistors （MOS-HEMTs） employing a 3-nm ultra-thin atomic-layer deposited （ALD） Al2O3 gate dielectric layer are reported. Devices with 0.6μm gate lengths exhibit an improved maximum drain current density of 1227mA/mm at a gate bias of 3 V, a peak transeonductance of 328mS/mm, a cutoff frequency fr of 16 GHz, a maximum frequency of oscillation fmax of 45 GHz, as well as significant gate leakage suppression in both reverse and forward directions, compared with the conventionM Al0.85In0.15N/AlN/GaN HEMT. Negligible C - V hysteresis, together with a smaller pinch-off voltage shift, is observed, demonstrating few bulk traps in the dielectric and high quality of the Al2O3/AIInN interface, it is most notable that not only the transconductance profile of the MOS-HEMT is almost the same as that of the conventional HEMT with a negative shift, but also the peak transconduetance of the MOS-HEMT is increased slightly. It is an exeitin~ inwrovement in the transconductance performance.