6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

Investigation of a 4H-SiC metal-insulation-semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited(ALD) Al2O3 /dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8°off-axis 4H-SiC(0001) epitaxial wafers are investigated in this paper.The metal-insulation-semiconductor(MIS) capacitors,respectively with different gate dielectric stacks(Al2O3/SiO2,Al2O3,and SiO2) are fabricated and compared with each other.The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field(≥12 MV/cm) comparable to SiO2,and a relatively low gate leakage current of1×10-7A/cm2 at an electric field of4 MV/cm comparable to Al2O3.The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage,indicating a less effective charge and slow-trap density near the interface.     

4H-SiC Schottky barrier diodes with semi-insulating polycrystalline silicon field plate termination

Based on the theoretical analysis of the 4H-SiC Schottky-barrier diodes(SBDs) with field plate termination, 4H-SiC SBD with semi-insulating polycrystalline silicon(SIPOS) FP termination has been fabricated. The relative dielectric constant of the SIPOS dielectric first used in 4H-SiC devices is 10.4, which is much higher than that of the SiO2dielectric,leading to benefitting the performance of devices. The breakdown voltage of the fabricated SBD could reach 1200 V at leakage current 20 μA, about 70% of the theoretical breakdown voltage. Meanwhile, both of the simulation and experimental results show that the length of the SIPOS FP termination is an important factor for structure design.     

N型4H-SiC低温拉曼光谱特性

利用拉曼散射技术对N型4H-SiC单晶材料进行了30～300 K温度范围的光谱测量。实验结果表明,随着温度的升高,N型4H-SiC单晶材料的拉曼峰峰位向低波数方向移动,峰宽逐渐增宽。分析认为,晶格振动随着温度的升高而随之加剧,其振动恢复力会逐渐减小,使振动频率降低;原子相对运动会随温度的升高而加剧,使得原子之间及晶胞之间的相互作用减弱,致使声学模和光学模皆出现红移现象。随着温度的升高,峰宽逐渐增宽。这是由于随着温度的升高声子数逐渐增加,增加的声子进一步增加了散射概率,从而降低了声子的平均寿命,而声子的平均寿命与峰宽成反比,因此随着温度的升高峰宽逐渐增宽。声子模强度随温度升高呈现不同规律,E₂(LA),E₂(TA),E₁(TA)和A₁(LA)声子模随着温度升高强度单调增加,而E₂(TO),E₁(TO)和A₁(LO)声子模强度出现了先增后减的明显变化,在138 K强度出现极大值。分析认为造成原因是由于当温度高于138 K时,高能量的声子分裂成多个具有更低能量的声子所致。     

Simulation study of a mixed terminal structure for 4H-SiC merged PiN/Schottky diode

In this paper, a mixed terminal structure for the 4H-SiC merged PiN/Schottky diode (MPS) is investigated, which is a combination of a field plate, a junction termination extension and floating limiting rings. Optimization is performed on the terminal structure by using the ISE-TCAD. Further analysis shows that this structure can greatly reduce the sensitivity of the breakdown voltage to the doping concentration and can effectively suppress the effect of the interface charge compared with the structure of the junction termination extension. At the same time, the 4H-SiC MPS with this termination structure can reach a high and stable breakdown voltage.     

Temperature-dependent characteristics of 4Hben SiC junction barrier Schottky diodes

The current-voltage characteristics of 4H-SiC junction barrier Schottky (JBS) diodes terminated by an offset field plate have been measured in the temperature range of 25-300 ℃. An experimental barrier height value of about 0.5 eV is obtained for the Ti/4H-SiC JBS diodes at room temperature. A decrease in the experimental barrier height and an increase in the ideality factor with decreasing temperature are shown. Reverse recovery testing also shows the temperature dependence of the peak recovery current density and the reverse recovery time. Finally, a discussion of reducing the reverse recovery time is presented.     

A CAD oriented quasi-analytical large-signal drain current model for 4H-SiC MESFETs

This paper reports that a 4H-SiC MESFET (Metal Semiconductor Field Effect Transistor) large signal drain current model based on physical expressions has been developed to be used in CAD tools. The form of drain current model is based on semi-empirical MESFET model, and all parameters in this model are determined by physical parameters of 4H-SiC MESFET. The verification of the present model embedded in CAD tools is made, which shows a good agreement with measured data of large signal DC I-V characteristics, PAE (power added efficiency), output power and gain.     

4H-SiC同质外延生长Grove模型研究

本文通过对4H-SiC同质外延化学反应和生长条件的分析,建立了4H-SiC同质外延生长的Grove模型,并结合实验结果进行了分析和验证.通过理论分析和实验验证,得到了外延中氢气载气流量和生长温度对4H-SiC同质外延生长速率的影响.研究表明:外延生长速率在衬底直径上为碗型分布,中心的生长速率略低于边缘的生长速率;随着载气流量的增大,生长速率由输运控制转变为反应速率控制,生长速率先增大而后逐渐降低;载气流量的增加,会使高温区会发生漂移,生长速率的理论值和实验出现一定的偏移;随着外延生长温度的升高,化学反应速率和气相转移系数都会增大,提高了外延速率;温度对外延反应速率的影响远大于对生长质量输运的影响,当温度过分升高后,外延生长会进入质量控制区;但过高的生长温度导致源气体在生长区边缘发生反应,生成固体粒子,使实际参与外延生长的粒子数减少,降低了生长速率,且固体粒子会有一定的概率落在外延层上,严重影响外延层的质量.通过调节氢气流量,衬底旋转速度和生长温度,可以有效的控制外延的生长速度和厚度的均匀性.     

基于碳化硅等离子体器件的功率脉冲锐化技术

利用Sentaurus搭建了碳化硅漂移阶跃恢复二极管（DSRD）与雪崩整形二极管（DAS）全电路仿真模型,研究了碳化硅等离子体器件在脉冲锐化方面的能力,并且通过器件内部等离子浓度分布解释了这两种器件实现脉冲锐化的机制。借助碳化硅DSRD可以将峰值超过千伏的电压脉冲的前沿缩短到300 ps;碳化硅DSRD与DAS的组合可以输出脉冲前沿在35 ps、峰值超过2 kV的电压脉冲。仿真与实验发现当触发脉冲与碳化硅DAS匹配时,可以实现快速开启后快速关断,得益于碳化硅DAS这种神奇现象,可以将峰值在两千伏以上脉冲的半高宽缩小到百皮秒量级;通过频谱分析发现脉冲经过DAS整形后,其最高幅值-30 dB对应的频谱带宽扩大了37倍,达到7.4 GHz。     

Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO

Near-interface oxide traps(NIOTs)in 4H–Si C metal–oxide–semiconductor(MOS)structures fabricated with and without annealing in NO are systematically investigated in this paper.The properties of NIOTs in Si C MOS structures prepared with and without annealing in NO are studied and compared in detail.Two main categories of the NIOTs,the"slow"and"fast"NIOTs,are revealed and extracted.The densities of the"fast"NIOTs are determined to be 0.76×10~(11)cm~(-2)and0.47×10~(11)cm~(-2)for the N_2 post oxidation annealing(POA)sample and NO POA sample,respectively.The densities of"slow"NIOTs are 0.79×10~(11)cm~(-2)and 9.44×10~(11)cm~(-2)for the NO POA sample and N_2POA sample,respectively.It is found that the NO POA process only can significantly reduce"slow"NIOTs.However,it has a little effect on"fast"NIOTs.The negative and positive constant voltage stresses(CVS)reveal that electrons captured by those"slow"NIOTs and bulk oxide traps(BOTs)are hardly emitted by the constant voltage stress.