Providing secure execution environments with a last line of defense against Trojan circuit attacks

Integrated circuits (ICs) are often produced in foundries that lack effective security controls. In these foundries, sophisticated attackers are able to insert malicious Trojan circuits that are easily hidden in the large, complex circuitry that comprises modern ICs. These so-called Trojan circuits are capable of launching attacks directly in hardware, or, more deviously, can facilitate software attacks. Current defense against Trojan circuits consists of statistical detection techniques to find such circuits before product deployment. The fact that statistical detection can result in false negatives raises the obvious questions: can attacks be detected post-deployment, and is secure execution nonetheless possible using chips with undetected Trojan circuits? In this paper we present the Secure Heartbeat And Dual-Encryption (SHADE) architecture, a compiler–hardware solution for detecting and preventing a subset of Trojan circuit attacks in deployed systems. Two layers of hardware encryption are combined with a heartbeat of off-chip accesses to provide a secure execution environment using untrusted hardware. The SHADE system is designed to complement pre-deployment detection techniques and to add a final, last-chance layer of security.     

Recommendation engine based on derived wisdom for more similar item neighbors

Information Systems and e-Business Management - Collaborative filtering (CF) is a popular and widely accepted recommendation technique. CF is an automated form of word-of-mouth communication...     

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file.We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine.     

Compact modeling of amorphous‐silicon thin‐film transistors with BSIM3

Abstract— A novel approach of modeling a‐Si:H TFTs with the industry‐standard BSIM3 compact model is presented. The described approach defines the a‐Si:H TFT drain current and terminal charges as explicit functions of terminal voltages using a minimum set of BSIM3 parameters. The set of BSIM3 parameters is chosen based on the electrical and physical characteristics of the a‐Si:H TFT and their values extracted from measured data. By using the selected BSIM3 model parameters, the a‐Si:H TFT is simulated inside SPICE to fit the simulated I‐V and C‐V curves with the measured results. Finally, the extracted BSIM3 model is validated by simulating the kickback voltage effect in an AMLCD pixel array.     

Shape Morphing-Based Control of Robotic Visual Servoing

We present an approach for controlling robotic interactions with objects, using synthetic images generated by morphing shapes. In particular, we attempt the problem of positioning an eye-in-hand robotic system with respect to objects in the workspace for grasping and manipulation. In our formulation, the grasp position (and consequently the approach trajectory of the manipulator), varies with each object. The proposed solution to the problem consists of two parts. First, based on a model-based object recognition framework, images of the objects taken at the desired grasp pose are stored in a database. The recognition and identification of the grasp position for an unknown input object (selected from the family of recognizable objects) occurs by morphing its contour to the templates in the database and using the virtual energy spent during the morph as a dissimilarity measure. In the second step, the images synthesized during the morph are used to guide the eye-in-hand system and execute the grasp. The proposed method requires minimal calibration of the system. Furthermore, it conjoins techniques from shape recognition, computer graphics, and vision-based robot control in a unified engineering amework. Potential applications range from recognition and positioning with respect to partially-occluded or deformable objects to planning robotic grasping based on human demonstration.     

FireFly: a cross-layer platform for real-time embedded wireless networks

We propose a cross-layer approach with tightly-coupled time synchronization for real-time support and predictable lifetime in battery-operated sensor networks. Our design spans a sensor hardware platform with hardware-based global time synchronization, a TDMA link layer protocol with collision-free multi-hop support and node scheduling algorithms for maximum concurrency and streaming. Our dual-radio sensor platform, FireFly, features an IEEE 802.15.4 transceiver and supports global time synchronization indoors by using an AM radio carrier-current method and an atomic clock receiver for outdoors. A TDMA-based link protocol, RT-Link, leverages the hardware for fixed and mobile nodes with a near-optimal and predictable node lifetime of over 2 years. It outperforms comparable sensor network link protocols such as B-MAC and S-MAC in terms of end-to-end latency and throughput and node lifetime across all duty cycle ratios. Operating over RT-Link is MAX, a scheduling framework which offers optimal transmission concurrency and bandwidth management for networks with regular structure. Through analysis and experiments we show that global time sync is a robust, economical and scalable alternative to in-band software-based techniques. To illustrate the capabilities and flexibility of our platform, we describe our experiences with two-way voice streaming over multiple hops. We have deployed a 42-node network with sub-100 μs synchronization accuracy in the NIOSH experimental coal mine for people-tracking and voice communication.

Homology modeling of the DNA-binding domain of human Smad5: a molecular model for inhibitor design

Members of the Smad protein family function as signal transducers of the transforming growth factor (TGF-beta) superfamily proteins. The human Smad5 protein, a signal transducer downstream of TGF-beta/BMP receptors, is composed of N-terminal DNA binding domain (MH1) and C-terminal protein-protein interaction domain (MH2) connected together by a linker motif. We used homology-modeling techniques to generate a reliable molecular model of the Smad5 MH1 domain based on the crystal structure of Smad3 MH1 domain. Our study presents the structural features of a BMP-regulated, R-Smad subfamily member (consisting of Smad1, Smad5 and Smad8) for the first time. This model provides a structural basis for explaining both functional similarities and differences between Smad3 and Smad5. Also, the structural model of this molecular target would be useful for structure-based inhibitor design because of its high accuracy. The results of our study provide important insights into understanding the structure-function relationship of the members of the Smad protein family and can serve to guide future genetic and biochemical experiments in this area.     

A Framework and Lightweight Protocol for Multimedia Network Management

The increasing complexities of modern networks coupled with the popularity of multimedia applications have placed higher demands on network managers. This paper reviews the main requirements and challenges for effective management of multimedia networks, presents a case study of a thin-client-based multimedia system called CSL (Computer-supported Learning System) and proposes a framework for managing such networks. CSL delivers browser-based assessments and other learning materials to thousands of students at the University of Auckland. This type of demand requires more flexible schemes for the management of the network. In the framework proposed, most of the link management information will be kept in a MIB in the network and a very simple MIB will be maintained in the thin client. The MIB in the network is accessible to the network management application, and a lightweight protocol is proposed for updating of the network MIB using an agent at the thin client.     

Electrical conduction measurements in solution-mixed polyblends of poly(vinylidene fluoride) and poly(methylmethacrylate)

The d.c.-electrical conductivity studies have been done in poly(vinylidene fluoride) (PVDF), poly(methylmethacrylate) (PMMA) and their polyblends in the entire composition range as a function of voltage and temperature. Some studies on thickness and electrode dependence of the electrical conductivity were also carried out. The results obtained show that the charge carriers are generated by Richardson-Schottky emission from the electrode as well as from trapped ionic impurities at high fields and are conducted through the bulk of the material by a carrier hopping process. The values of Schottky field lowering constant _RS, the Poole-Frenkel trap lowering constant _PF, the effective metal insulator potential barrier, the ionic jump distance and the activation energy involved in the conduction process are reported. A.c.-conductivity values were calculated from a.c.-dielectric data and the results show the evidence of hopping conduction in the bulk of polyblends.     

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy–performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy–delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure.