涡轮搅拌桨反应器混合过程的数值计算

利用CFD方法计算单层涡轮反应器搅拌槽内流体混合过程的速度场和浓度场,研究物料在搅拌槽内的混合过程,以及不同监测点对混合时间的影响。结果表明,搅拌槽内物料的混合主要受槽内流体的流动形式所影响;混合时间的长短与监测点位置有关;在搅拌桨的桨叶附近进行监测所得到的混合时间较短,在液面附近进行监测所得的混合时间较长。在实际生产和试验中,应注意对监测点位置的选取。     

现场总线漫谈

从现场总线多标准的现状出发，阐述了控制对象多样性与技术多样性之间的必然联系，通过对目前现场总线与传统DCS应用现状的分析，对现场总线的发展和应用前景进行了展望。     

加氢反应器制造技术的新进展

随着加氢装置的大型化,对加氢反应器的设计、主体材质的选用及制造均提出了新的、更高的要求。文章较全面地介绍了国内外加氢反应器的设计准则、主体材质(抗氢钢)和制造技术等方面的新进展。     

北部湾盆地福山凹陷CO2气成因探讨

北部湾盆地福山凹陷油气钻探中发现了高含CO₂气的天然气气藏。对CO₂气稳定碳同位素、伴生稀有气体氦和氩同位素进行了分析研究，结果显示，福山凹陷CO₂气稳定碳同位素偏重，(13C_CO2为-5.01～-10.08‰，绝大多数样品大于-7.0‰，为无机成因CO₂气特征；伴生稀有气体氦同位素³He/⁴He值为(4.74~5.03)×10^-6，R/Ra值为3.38～3.59；伴生稀有气体氩同位素⁴⁰Ar/³⁶Ar值为1881～2190，也显示出幔源或壳幔混合CO₂气的特征。综合判定认为，福山凹陷CO₂为壳幔混合成因。始新统流沙港组岩浆岩体分布特征与CO₂气藏分布范围基本一致，也表明幔源-岩浆可能是福山凹陷CO₂气的主要来源。与南海北部边缘盆地其它地区如珠江口盆地西部、琼东南盆地东部CO₂气成因一致，都为幔源-岩浆来源，或壳幔混合来源。     

含硫化氢气井钻井过程中的腐蚀因素与防护研究

在含硫气井的钻井过程中对于HRC大于22的钻具钢材除了腐蚀疲劳之外，在pH值小于9的环境中会发生硫化物应力腐蚀破裂，这种破坏比腐蚀疲劳更突然、更快，使钻杆大量损坏。含硫气井在钻井过程中，由于湿硫化氢的出现，常常会出现油管、套管、钻井设备、钻井仪器以及对支持保护管柱的水泥环柱等腐蚀和损坏问题，为此，阐述了湿硫化氢的腐蚀特点、机理，归纳总结了影响腐蚀的因素，综述了如何在这些方面防止其腐蚀，使损失减小，为指导油管、套管防腐工程实践提供了依据。建议在钻井过程中采用碱性钻井液，其pH值可到9或更高(至pH值12)，以减缓或防止钻井过程中电化学从硫化物应力腐蚀破裂；含硫气井用的钻杆应该间歇使用。钻杆停用堆置时间可使其放氢，使钻杆恢复韧性，防止硫化物应力腐蚀断裂。     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.     

Degree-of-polarization and eye-closure penalty associated with optical signals with orthogonal polarizations

We perform a systematic measurement of the degree-of-polarization (DOP) and eye-closure penalty for optical signals with orthogonal polarizations. We find that the symmetry of DOP is maintained for the orthogonal polarizations under both first and higher order polarization-mode dispersion (PMD), whereas the symmetry of eye-closure penalty is broken under second-order PMD. An orthogonal polarization pair can have large disparity of eye-closure penalty despite an identical DOP. We also demonstrate a novel approach to estimate the maximum eye-closure penalty asymmetry with three orthogonal polarizations on the Poincare/spl acute/ sphere.     

Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms     

A New Hand-Held Microsystem Architecture for Biological Analysis

This paper presents a hand-held microsystem based on new fully integrated magnetoresistive biochips for biomolecular recognition (DNA hybridization, antibody antigen interaction, etc.). Magnetoresistive chip surfaces are chemically treated, enabling the immobilization of probe biomolecules such as DNA or antibodies. Fluid handling is also integrated in the biochip. The proposed microsystem not only integrates the biochip, which is an array of 16times16 magnetoresistive sensors, but it also provides all the electronic circuitry for addressing and reading out each transducer. The proposed architecture and circuits were specifically designed for achieving a compact, programmable and portable microsystem. The microsystem also integrates a hand-held analyzer connected through a wireless channel. A prototype of the system was already developed and detection of magnetic nanoparticles was obtained. This indicates that the system may be used for magnetic label based bioassays     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.