Decorative near-infrared transmission filters featuring high-efficiency and angular-insensitivity employing 1D photonic crystals

We present a new scheme for visibly-opaque but near-infrared-transmitting filters involving 7 layers based on one-dimensional ternary photonic crystals, with capabilities in reaching nearly 100% transmission efficiency in the near-infrared region. Different decorative reflection colors can be created by adding additional three layers while maintaining the near-infrared transmission performance. In addition, our proposed structural colors show great angular insensitivity up to ±60° for both transverse electric and transverse magnetic polarizations, which are highly desired in various fields. The facile strategy described here involves a simple deposition method for the fabrication, thereby having great potential in diverse applications such as image sensors, anti-counterfeit tag, and optical measurement systems.

     

Frequency Insertion Strategy for Channel Assignment Problem

This paper presents a new heuristic method for quickly finding a good feasible solution to the channel assignment problem (CAP). Like many other greedy-type heuristics for CAP, the proposed method also assigns a frequency to a call, one at a time. Hence, the method requires computational time that increases only linear to the number of calls. However, what distinguishes the method from others is that it starts with a narrow enough frequency band so as to provoke violations of constraints that we need to comply with in order to avoid radio interference. Each violation is then resolved by inserting frequencies at the most appropriate positions so that the band of frequencies expands minimally. An extensive computational experiment using a set of randomly generated problems as well as the Philadelphia benchmark instances shows that the proposed method perform statistically better than existing methods of its kind and even yields optimum solutions to most of Philadelphia benchmark instances among which two cases are reported for the first time ever, in this paper. Won-Young Shin was born in Busan, Korea in 1978. He received B.S. in industrial engineering from Pohang University of Science and Technology (POSTECH) in 2001 and M.S in operation research and applied statistics from POSTECH in 2003. Since 2003 he has been a researcher of Agency for Defense Development (ADD) in Korea. He is interested in optimization of communication system and applied statistics. Soo Y. Chang is an associate professor in the Department of Industrial Engineering at Pohang University of Science and Technology (POSTECH), Pohang, Korea. He teaches linear programming, discrete optimization, network flows and operations research courses. His research interests include mathematical programming and scheduling. He has published in several journals including Discrete Applied Mathematics, Computers and Mathematics with Application, IIE Transactions, International Journal of Production Research, and so on. He is a member of Korean IIE, and ORMSS. Jaewook Lee is an assistant professor in the Department of Industrial Engineering at Pohang University of Science and Technology (POSTECH), Pohang, Korea. He received the B.S. degree in mathematics with honors from Seoul National University, and the Ph.D. degree from Cornell University in applied mathematics in 1993 and 1999, respectively. He is currently an assistant professor in the department of industrial engineering at the Pohang University of Science and Technology (POSTECH). His research interests include nonlinear systems, neural networks, nonlinear optimization, and their applications to data mining and financial engineering. Chi-Hyuck Jun was born in Seoul, Korea in 1954. He received B.S. in mineral and petroleum engineering from Seoul National University in 1977, M.S. in industrial engineering from Korea Advanced Institute of Science and Technology in 1979 and Ph.D. in operations research from University of California, Berkeley, in 1986. Since 1987 he has been with the department of industrial engineering, Pohang University of Science and Technology (POSTECH) and he is now a professor and the department head. He is interested in performance analysis of communication and production systems. He has published in several journals including IIE Transactions, IEEE Transactions, Queueing Systems and Chemometrics and Intelligent Laboratory Systems. He is a member of IEEE, INFORMS and ASQ.     

Identification of the adverse effect of nitrate on the phosphate release rate and improvement of EBPR process models.

The adverse effect of nitrate on the phosphate release rate in the anaerobic phase was observed and was hardly explainable with conventional EBPR process models. Four possible mechanisms were proposed including substrate competition, reduced fermentation, parallel reaction and sequential reaction. Batch experiments were designed and conducted to identify the dominant mechanism. Results showed that the sequential reaction was the only possible mechanism where only denitrification occurred if any nitrate existed in the anaerobic phase. Then the phosphate release following after the nitrate was completely removed. Nitrate inhibition effect was added into the PHA storage rate to incorporate the sequential reaction in the conventional ASM3 plus EAWAG bio-P module (ASM3 + P). Nitrate inhibition coefficient, K(I,NO,PAO) was found to be as low as 0.05 mg/L. This correlated well with experimental observation where no also meant that the anaerobic compartment of a continuous flow reactor could be seriously affected by the residual nitrate contained in the sludge recycle flow. This phenomenon caused overestimation of the phosphate uptake rate and consequently underestimation of PO4(3-) -P concentration. This problem was resolved by incorporation of a nitrate inhibition term in the ASM3 + P for more accurate simulation of the EBPR process.     

基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

Effect of modified atmosphere packaging on the shelf-life of coated, whole and sliced mushrooms

Whole and sliced fresh mushrooms (Agaricus bisporus) were packaged with PVC wrap or two polyolefins (PD-941 and PD-961) films after coating with CaCl₂ and chitosan. Package gas composition, color, weight loss and maturity were measured during storage at 12 °C and 80%RH. For PD-961, the highest in-package concentration occurred during the first day of storage regardless of treatments, while wrap and PD-941 showed varying degrees in-package concentration with different processes and coatings. The whiteness of whole mushrooms varied significantly with the type of coating, but not with the type of films. The extent of darkening was greater in coated whole mushrooms than in sliced ones. Weight loss occurred in all packages and varied from 3 (g/100 g) to about 7 (g/100 g) after 6 days of storage. Due to a lower permeability, PD-961 packages had the lowest weight loss. The type of packaging films significantly affected the maturity index, where PD-961 most effectively lowered maturity index for both whole and sliced mushrooms, thus extending the shelf-life. The type of coating did not appear to affect maturity index except for the wrap package where chitosan coating markedly lowered the maturity index of sliced mushrooms.