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This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amplitude detection and frequency detection,is proposed to reject interference and reduce false wake-ups.An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness.The circuit is fabricated in TSMC 0.18μm 3.3 V CMOS technology with an area of 0.12 mm2.Measurement results show that the sensitivity is -54.5 dBm with only a±0.95 dBm variation from the 1.8 to 3.3 V power supply,and that the temperature variation of the sensitivity is±1.4 dBm from -50 to 100℃. The current consumption is 1.4 to 1.7μA under a 1.8 to 3.3 V power supply. 相似文献
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This paper presents a novel dual-band quadrature voltage controlled oscillator(VCO) with the gain proportional to the oscillation frequency.Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration.Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO.The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived.For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with±16%variation over the entire frequency range.The phase noise is -138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and -137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier. 相似文献
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A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes: mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 μm CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively. 相似文献
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