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共晶合成料的特点及在锰锌铁氧体生产中的应用 总被引:2,自引:0,他引:2
通过工艺流程的比较、X射线衍射分析、电子探针和微区分析,对共晶合成料的特点进行了研究。结果表明:共晶合成料物理、化学特性好,一致性和可控性较佳。其自身的特点决定了其工艺流程尚不能取消预烧工序。共晶合成法生产的高磁导率材料频段在10-100kHz时μi〉12000,功率材料产品性能达到了日本TDK牌号为PC44的材料水平。 相似文献
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This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s). 相似文献
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为了提高无源超高频(UHF)射频识别(RFID)标签的灵敏度和增大工作距离,设计了一种高灵敏度的ASK解调器。在该解调器的包络检波电路中,采用了开启电压补偿技术,以减小电荷传输管的导通压降;并设计了一种无二极管无电阻的参考电平产生电路。基于0.18μm标准CMOS工艺实现了该解调器,其芯片面积为0.010 mm2,满足第2代第1类UHF RFID通讯协议(EPC C1G2)的要求。测试结果表明,当载波频率为900 MHz、调制深度为80%~100%、数据率为26.7~128 kbit/s时,解调器能够解调信号的能量强度范围为-16~+20 dBm。在工作电压为0.8 V时,其功耗仅为0.56μW。 相似文献
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面向无源超高频射频识别标签芯片设计了一种低成本的非易失存储器(NVM)。采用PMOS晶体管实现存储单元,制造工艺与标准CMOS工艺兼容,可以降低制造成本。提出了一种新型的操作模式,可减轻写操作对栅氧的破坏。存储器中的所有存储单元共享一个灵敏放大器,数据通过共享的灵敏放大器依次串行读出,这样既节省了面积,又降低了读操作的功耗。基于0.18μm标准CMOS工艺设计实现了存储容量为1 kbit的存储器芯片,该存储器的核心面积为0.095 mm2,并完成了实测。实测结果表明,电源电压为1.2 V,读速率为1 Mb/s时,功耗为1.08μW;写速率为3.2 kb/s时,功耗为44μW。 相似文献
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This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm2 and 0.12 mm2, respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V. The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s). 相似文献