一种用于预放大器的平均电阻网络设计

基于预放大器阵列,设计了一种用于解决电压失调的平均电阻网络。分析了电阻网络边界效应产生的原因。采用冗余预放大器设计、环形平均网络设计,并提出非等值终端电阻设计缓解边界效应。提出节点矩阵电流方程,为平均电阻网络的设计提供优化方向。在采用节点矩阵电流方程改善边界效应后,将该预放大器阵列用于12 bit的折叠插值ADC中,在2.5 GSPS采样频率、1.242 GHz的0.8 V正弦输入下,得到ADC的ENOB为10.32 bits,SFDR为74.3 dB。     

嵌入式折叠内插式CMOS模/数转换器设计

基于折叠内插式 ADC结构 ,采用分段式结构、两级折叠、主动内插技术和非线性误差补偿技术 ,采用TSMC0 .35 μm CMOS工艺设计实现了 8位 40 MS/s ADC。基于 BSIM3V3模型 ,采用 Cadence Spectre仿真器对 8位折叠内插式 ADC进行了系统仿真 ,采用 MPW计划对 ADC进行了流片验证 ,仿真和测试结果表明该ADC具有较低的非线性误差和良好的频域特性 ,证明了误差补偿技术的有效性。该 ADC的有效面积为 0 .6mm2 ,适合嵌入式应用。     

一种8位1 GS/s折叠内插A/D转换器

基于TSMC 0.18 μm CMOS工艺,采用两级级联的折叠内插结构,设计了一种8位1 GS/s折叠内插A/D转换器。在预放大器阵列输出端引入失调平均网络,优化了预放大器阵列的输入对管尺寸,以补偿边界预放大器的增益衰减。在折叠电路中引入幅度补偿电路,以增加较小的电路功耗为代价改善了电路的带宽限制,提高了增益及输出线性范围。分析了内插平均电阻网路中的高倍内插误差,通过优化内插电阻值,实现了内插输出失调的减小,保证了系统良好的精度特性。仿真结果表明,在采样率为1 GS/s、输入正弦波频率为465.82 MHz的条件下,该8位折叠内插A/D转换器的有效位数能够达到7.31位,功耗为290 mW。     

12位800 MS/s ADC设计

提出了一种基于0.18 μm CMOS工艺设计的12位800 MS/s高速ADC。采用独特的折叠/内插与流水线相组合的结构,兼具折叠/内插结构的高转化率与流水线结构的高分辨率的优点。介绍了ADC的总体结构,分析了采样保持电路的设计原理,阐述了折叠/插值与流水线结构电路的机理,描述了数字自校正原理。在采样率800 MS/s和模拟输入397 MHz条件下进行版图后仿真,SFDR达到62 dB。     

基于90nm CMOS工艺的2GS/s 8-bit 折叠插值ADC的设计*

本文基于90nm CMOS工艺设计了一个单通道 2GSPS, 8-bit 折叠插值模数转换器。本设计采用折叠级联结构,通过在折叠电路间增加级间采样保持器的方法增加量化时间。电路中采用了数字前台辅助校正技术以提高信号的线性度。后仿结果表明,在奈奎斯特采样频率,该ADC的微分非线性DNL<±0.3LSB,积分非线性INL<±0.25LSB,有效位数达到7.338比特。包括焊盘在内的整体芯片面积为880×880 μm2。电路在1.2V 电源电压下功耗为210mW.     

折叠内插式模/数转换器误差补偿技术研究

分析了高速折叠内插式ADC结构和各种影响ADC性能的因素，基于自动调零技术原理，在前置放大器与折叠放大器之间引入差分对，实现放大器失调电压的补偿。基于补偿技术，实现了8位补偿的折叠内插式ADC，采用Star-Sim对8位补偿ADC进行仿真，仿真结果与典型的8位ADC进行比较，证明了自动调零补偿技术能明显改善折叠内插式ADC的线性误差，也可适合应用于其它高速ADC的误差补偿。     

一种基于平均电阻网络的预放大级设计

平均电阻网路的引入会给预放大器带来增益、延时误差、边界效应等问题。通过从中间向两边依次增加预放大器输入对管的尺寸,减小整体误差。通过改变环形平均电阻的边界阻值和边缘放大器的输入参考电压,减小边界效应,并且使用的边缘放大器数目较少。采用TSMC 0.18 μm标准CMOS工艺,在1.8 V电源电压下,对加入平均电阻网络的ADC的输出进行仿真,得到INL为1.01 LSB、DNL为0.573 LSB。对改变输入对管尺寸的ADC整体电路进行DFT分析,得到ENOB为11.14 bit、SFDR为76.3 dB、THD为-78 dB。采用减小边界效应的方法,对边界预放大器进行蒙特卡洛仿真,结果表明,失调电压方差从2.193 mV减小到0.456 mV。     

基于∑-ΔADC的低功耗运算放大器设计

介绍了一种用于∑-ΔADC的低功耗运算放大器电路。该电路采用全差分折叠-共源共栅结构,采用0.35μm CMOS工艺实现,工作于3 V电源电压。仿真结果表明,该电路的动态范围为80 dB、直流增益68 dB、单位增益带宽6.8 MHz、功耗仅为87.5μW,适用于∑-ΔADC。     

基于∑-△ ADC的低功耗运算放大器设计

介绍了一种用于∑-△ADC的低功耗运算放大器电路.该电路采用全差分折叠-共源共栅结构,采用0.35 μm CMOS工艺实现,工作于3 V电源电压.仿真结果表明,该电路的动态范围为80 dB、直流增益68 dB、单位增益带宽6.8 MHz、功耗仅为87.5 μW,适用于∑-△ ADC.     

折叠内插模数转换器分析及实现

应用Matlab/Simulink工具对折叠内插模数转换器进行了建模,研究了具有8bit分辨率、200MHz采样频率的该模数转换器的芯片设计和实现.系统设计时采用Matlab/Simulink进行行为级建模并分别分析了预放大的增益、折叠电路的带宽以及比较器的失调对动态性能的影响.设计实现的模数转换器实测结果表明,积分非线性误差和微分非线性误差分别小于0.77和0.6LSB,在采样频率为200MHz及输入信号频率为4MHz时,信号与噪声及谐波失真比为43.7dB.电路采用标准0.18μm CMOS数字工艺实现,电源电压为3.3V,功耗181mW,芯核面积0.25mm2.     

Cascaded voting process for flash ADC with interpolating scheme

A 3-stage cascaded voting process is proposed for flash analogue-todigital converters (ADCs) with an interpolation factor of 4 to eliminate the consecutive bubbles at the output nodes of the comparator array. Compared to the conventional 3-input voting process, the proposed process completely eliminates up to seven consecutive bubbles without hardware overhead, if the preamplifier output is assumed to have a single bubble at most. The proposed voting process is evaluated by 7-bit 1 GS/s CMOS flash ADCs with an interpolation factor of 4 which is designed by a 0.13 μm CMOS process with 1.2 V supply.     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

A 16-bit low-voltage CMOS A/D converter

A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.     

CDKF在GPS/SINS组合导航系统非线性模型中的应用

GPS/SINS组合导航系统模型的非线性会导致扩展卡尔曼滤波（EKF）的估计精度降低。而中心差分卡尔曼滤波（CDKF）的新型非线性滤波方法,则利用插值公式对非线性系统的状态估计进行逼近,从而减小线性化误差对系统精度的影响。针对GPS/SINS导航系统的特点,建立了一种非线性误差模型,并将EKF与CDKF分别应用于组合导航系统模型中进行仿真比较。仿真结果表明,该算法简单易实现,且能满足系统在非线性模型下的导航要求,并具有较高的精度和收敛性。     

移动数字电视接收机中宽带RF RSSI的设计

基于UMC 0.18 μm RF CMOS工艺,设计并实现了一个应用于移动数字电视接收机射频前端的接收信号强度指示仪(RF RSSI).提出了一种全新的功率检测电路,相对于传统的非平衡源级耦合对整流器,具有设计简单、功耗低以及良好的宽带功率指示功能;电路中前置放大器采用恒定跨导(G<,m>)偏置技术,输出放大器为三运放...     

A 15-b, 5-Msample/s low-spurious CMOS ADC

A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit (MSB) stages are digitally calibrated to implement a 15-b, 5-Msample/s low-spurious ADC using 1.4-μm CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC's in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components are suppressed to below -93 dB when sampled at 5 MHz. The chip occupies 27 mm², and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity (DNL) and 2 b in integral nonlinearity (INL) in a flash analog-to-digital converter (ADC). Fabricated in a 0.5-μm, triple-metal, single-poly CMOS process, the circuit measures 1.4 mm×1.4 mm including a bandgap and a sample-and-hold (SH), while the ADC itself occupies 1-mm². At a conversion rate of 50-MS/s the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB S/(N+D) with a 12-MHz 90% full-scale input     

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.     

Controlled nonlinearity monolithic integrated optoelectronic mixingreceiver

A monolithic integrated optoelectronic mixing receiver with low conversion loss is demonstrated. It consists of a GaAs metal-semiconductor-metal (MSM) photodetector mixer and a two-stage transimpedance preamplifier. By modulating the bias of the MSM photodetector with a local oscillator, the information signal on an optical carrier is down-converted to an electrical intermediate frequency. The mixing receiver nonlinearity can be controlled by simply changing the bias values to the MSM photodetector. The optoelectronic mixer has applications in subcarrier-multiplied lightwave distribution systems