A triggerable latch using a "Hybrid-mode" MOSFET bistable circuit

The potentialities which result from exploiting both types of conduction mechanism (majority and minority carriers) possible with an insulated-gate FET are exemplified in the design of a simple "hybrid-mode" regenerative circuit constituting a triggerable latch, which is switched on following the closure of two contacts and switched off via a separate input. The circuit is TTL-logic compatible and useful for such applications as touch-sensitive switching.     

含两个荷控忆阻器的五阶混沌电路研究

忆阻器作为一种具有记忆功能的新型非线性元件,被广泛应用于非线性电路系统设计中。利用两个基于荷控光滑模型的忆阻器以及采用常见的线性电子元件电感、电容、负电阻等设计了一种新的五阶混沌振荡电路。采用常规的系统动力学分析方法,分析了系统平衡点稳定性、相图、李雅普诺夫指数谱和分叉图,研究了系统随电路参数和荷控忆阻器初始状态变量变化的非线性动力学特性。Matlab数值仿真结果验证了理论分析的正确性。     

含两个磁控忆阻器的五阶混沌电路设计

基于经典蔡氏混沌振荡电路,利用2个磁控光滑忆阻器以及电容、电感设计了一种新的五阶混沌振荡电路。讨论了平衡点稳定性,分析了相图、Lyapunov指数和分岔图。此双忆阻混沌电路具有复杂的动力学行为,运动轨迹依赖于电路参数和电路初始状态;从能量的角度探索了奇异吸引子,结果表明系统存在不同吸引子共存的多稳态现象。用PSpice进行了电路设计,验证了Matlab理论仿真正确性和电路设计的可实现性。     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications

A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias control circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The adaptive bias control circuit detects the input power level and supplies a low quiescent current of 16 mA at the low output power level and an increased current up to 90 mA according to the increased power level adaptively. The intelligent W-CDMA power amplifier using the adaptive bias circuit exhibits an improvement of average power usage efficiency of more than 1.93 times, and an adjacent channel leakage ratio by 4 dB at the output power of 28.3 dBm.     

量子触发器的设计与优化

量子触发器是量子逻辑电路中一个很重要的量子器件,在量子计算领域有着重要的意义。根据量子触发器的逻辑功能,利用量子触发器输入和输出之间的关系,研究了一种通过引入辅助比特来解决数字电路反馈问题以及实现数据保持状态锁存功能的方法。设计构造了五种不同的量子触发器并对量子线路进行了优化。这些量子锁存器在建造量子计算机中可以作为可扩展的基本锁存功能单元使用。     

Low-power sequential circuit design using T flip-flops

This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by using T flip-flops. The unwanted triggering action of the master clock to flip-flops can be isolated during T = 0. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.     

一种基于三联锁结构的单粒子翻转加固锁存器

本文提出了一种基于三联锁结构的单粒子翻转加固锁存器。该锁存器使用保护门和反相器在其内部构建三路反馈,以此获得对发生在任一电路节点上的单粒子效应的自恢复能力,有效抑制由粒子轰击半导体引发的电荷沉积带来的影响。本文在详细分析已报道的三种抗辐射锁存器结构可靠性的基础上,针对其在单粒子效应作用下,或单粒子效应和耦合串扰噪声的共同作用下依然可能发生翻转的问题,指出本文提出的锁存器可通过内部的三联锁结构对上述问题进行有效的消除。所有结论均得到电路级单粒子效应注入仿真结果,以及基于经典串扰模型模拟串扰耦合和单粒子效应共同作用的仿真结果的支持和验证。     

An improved GaAs MESFET equivalent circuit model for analog integrated circuit applications

An improved equivalent circuit model of a gallium-arsenide (GaAs) MESFET that is optimized for the design and analysis of precision analog integrated circuits is described. These circuits entail different modeling requirements from digital or microwave circuits, for which existing equivalent circuit models are optimized. Improved techniques are presented to model the drain-to-source conductance, device capacitance, and the functional dependence of drain-to-source current.     

Self-assembled metallic nanocrystal structures for advanced non-volatile memory applications

Nanocrystal (NC) based non-volatile memories are a leading candidate to replace conventional floating gate memory. Substituting the poly-silicon gate with a layer of discrete nanocrystals or nanodots provides increased immunity to charge loss. Metallic nanocrystals have been found to be advantageous over Si- or Ge-based approaches due to good controllability of the size distribution and the achievable NC densities as well as increased charge storage capacity of metallic nanocrystals. Sufficiently high NC densities have been achieved to demonstrate feasibility for sub-32 nm node non-volatile memory devices.     

State assignment optimization for synchronous sequential circuits using multiplexer modules

This paper presents an algorithmic procedure based on the SHR.method for determining optimal state assignments for synchronous sequential circuits with multiplexer modules and D-, T- or JK-flip-flop memory. The cost is defined as the number of necessary modules required for separate realization of the associated excitation functions. The algorithm has been applied to a number of published state tables and a list of the results obtaining is given.     

An inductor modeling and optimization toolbox for RF circuit design

This paper describes the SIDe-O toolbox and the support it can provide to the radio-frequency designer. SIDe-O is a computer-aided design toolbox developed for the design of integrated inductors based on surrogate modeling techniques and the usage of evolutionary optimization algorithms. The models used feature less than 1% error when compared to electromagnetic simulations while reducing the simulation time by several orders of magnitude. Furthermore, the tool allows the creation of S-parameter files that accurately describe the behavior of inductors for a given range of frequencies, which can later be used in SPICE-like simulations for circuit design in commercial environments. This toolbox provides a solution to the problem of accurately and efficiently optimizing inductors, which alleviates the bottleneck that these devices represent in the radio-frequency circuit design process.     

High performance energy efficient radiation hardened latch for low voltage applications

Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits show a lesser immunity against soft error, because of the smaller device node capacitances in nanoscale technologies and near-threshold voltage operation. Due to these reasons, the tolerance of the sequential circuits to SEUs is an important consideration in nanoscale near threshold CMOS design. This paper presents an energy efficient SEU tolerant latch. The proposed latch improves the SEU tolerance by using a clocked Muller- C and memory elements based restorer circuit. The parasitic extracted simulations using STMicroelectronics 65 nm CMOS technology show that by employing the proposed latch, an average improvement of ∼40% in energy delay product (EDP), is obtained over the recently reported latch. Moreover, the proposed latch is also validated in a TCAD calibrated PTM 32 nm framework and PTM 22 nm CMOS technology nodes. In 32 nm and 22 nm technologies, the proposed latch improves the EDP ∼12% and 59% over existing latches respectively.     

Rare earth-based high-k materials for non-volatile memory applications

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on La_xZr_1−xO_2−δ (x = 0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al₂O₃ cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.     

Integration of organic based Schottky junctions for crossbar non-volatile memory applications

Small size Schottky junctions using two different synthesized organic semiconductors (oligophenylenevinylenes) were integrated by standard UV lithography into crossbar arrays. The proposed integration scheme can be applied to a wide class of organics without affecting material properties. Current-voltage characteristics were studied in order to investigate which of the tested compounds could possibly reach the requirements for non-volatile memory applications. All the investigated devices displayed good rectifying properties, ranging from 10² to 10⁴. On the other hand, one of the compounds reveals higher conductivity and possible reasons for this behavior are discussed.     

An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.     

An effective nonreciprocal circuit for semiconductor laser-to-optical-fiber coupling using a YIG sphere

A practical nonreciprocal optical circuit for laser-diode (LD)-to-optical-fiber coupling in the 1.3-μm wavelength region is described. It consists of a yttrium iron garnet- (YIG) sphere graded-index (GRIN) rod lens and a polarizer. The YIG sphere can function not only as a Faraday rotator but also as an effective coupling lens. High coupling efficiency of more than -5 dB for a single-mode fiber, and more than -2 dB for a multimode fiber, is easily achievable. Alignment sensitivities and coupling characteristics of the proposed circuit are also discussed theoretically and experimentally. The increase in LD relative intensity noise (RIN), caused by light injected into the LD, is estimated using the reciprocal characteristics of LD-to-single-mode-fiber coupling. By comparing the LD-RIN increase in the proposed non-reciprocal circuit with that of the reciprocal, high isolation of about 32 dB is confirmed. The fact that reflected light from the proposed circuit has little influence on LD characteristics is also clarified.