A triggerable latch using a "Hybrid-mode" MOSFET bistable circuit

The potentialities which result from exploiting both types of conduction mechanism (majority and minority carriers) possible with an insulated-gate FET are exemplified in the design of a simple "hybrid-mode" regenerative circuit constituting a triggerable latch, which is switched on following the closure of two contacts and switched off via a separate input. The circuit is TTL-logic compatible and useful for such applications as touch-sensitive switching.     

含两个荷控忆阻器的五阶混沌电路研究

忆阻器作为一种具有记忆功能的新型非线性元件,被广泛应用于非线性电路系统设计中。利用两个基于荷控光滑模型的忆阻器以及采用常见的线性电子元件电感、电容、负电阻等设计了一种新的五阶混沌振荡电路。采用常规的系统动力学分析方法,分析了系统平衡点稳定性、相图、李雅普诺夫指数谱和分叉图,研究了系统随电路参数和荷控忆阻器初始状态变量变化的非线性动力学特性。Matlab数值仿真结果验证了理论分析的正确性。     

An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications

A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias control circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The adaptive bias control circuit detects the input power level and supplies a low quiescent current of 16 mA at the low output power level and an increased current up to 90 mA according to the increased power level adaptively. The intelligent W-CDMA power amplifier using the adaptive bias circuit exhibits an improvement of average power usage efficiency of more than 1.93 times, and an adjacent channel leakage ratio by 4 dB at the output power of 28.3 dBm.     

Low-power sequential circuit design using T flip-flops

This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by using T flip-flops. The unwanted triggering action of the master clock to flip-flops can be isolated during T = 0. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.     

An improved GaAs MESFET equivalent circuit model for analog integrated circuit applications

An improved equivalent circuit model of a gallium-arsenide (GaAs) MESFET that is optimized for the design and analysis of precision analog integrated circuits is described. These circuits entail different modeling requirements from digital or microwave circuits, for which existing equivalent circuit models are optimized. Improved techniques are presented to model the drain-to-source conductance, device capacitance, and the functional dependence of drain-to-source current.     

State assignment optimization for synchronous sequential circuits using multiplexer modules

This paper presents an algorithmic procedure based on the SHR.method for determining optimal state assignments for synchronous sequential circuits with multiplexer modules and D-, T- or JK-flip-flop memory. The cost is defined as the number of necessary modules required for separate realization of the associated excitation functions. The algorithm has been applied to a number of published state tables and a list of the results obtaining is given.     

Self-assembled metallic nanocrystal structures for advanced non-volatile memory applications

Nanocrystal (NC) based non-volatile memories are a leading candidate to replace conventional floating gate memory. Substituting the poly-silicon gate with a layer of discrete nanocrystals or nanodots provides increased immunity to charge loss. Metallic nanocrystals have been found to be advantageous over Si- or Ge-based approaches due to good controllability of the size distribution and the achievable NC densities as well as increased charge storage capacity of metallic nanocrystals. Sufficiently high NC densities have been achieved to demonstrate feasibility for sub-32 nm node non-volatile memory devices.     

Rare earth-based high-k materials for non-volatile memory applications

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on La_xZr_1−xO_2−δ (x = 0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al₂O₃ cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.     

Integration of organic based Schottky junctions for crossbar non-volatile memory applications

Small size Schottky junctions using two different synthesized organic semiconductors (oligophenylenevinylenes) were integrated by standard UV lithography into crossbar arrays. The proposed integration scheme can be applied to a wide class of organics without affecting material properties. Current-voltage characteristics were studied in order to investigate which of the tested compounds could possibly reach the requirements for non-volatile memory applications. All the investigated devices displayed good rectifying properties, ranging from 10² to 10⁴. On the other hand, one of the compounds reveals higher conductivity and possible reasons for this behavior are discussed.     

An effective nonreciprocal circuit for semiconductor laser-to-optical-fiber coupling using a YIG sphere

A practical nonreciprocal optical circuit for laser-diode (LD)-to-optical-fiber coupling in the 1.3-μm wavelength region is described. It consists of a yttrium iron garnet- (YIG) sphere graded-index (GRIN) rod lens and a polarizer. The YIG sphere can function not only as a Faraday rotator but also as an effective coupling lens. High coupling efficiency of more than -5 dB for a single-mode fiber, and more than -2 dB for a multimode fiber, is easily achievable. Alignment sensitivities and coupling characteristics of the proposed circuit are also discussed theoretically and experimentally. The increase in LD relative intensity noise (RIN), caused by light injected into the LD, is estimated using the reciprocal characteristics of LD-to-single-mode-fiber coupling. By comparing the LD-RIN increase in the proposed non-reciprocal circuit with that of the reciprocal, high isolation of about 32 dB is confirmed. The fact that reflected light from the proposed circuit has little influence on LD characteristics is also clarified.     

An improved sensorless driving method for SRM using a phase-shift circuit technique

This paper presents an improved sensorless driving method for switched reluctance motor (SRM) using a phase-shift circuit technique. The conventional method consists of impressing short voltage pulses during unenergized phases, measuring the phase current pulses, and finding the correlation between the filtered current signals and rotor position. However, the filtering process causes a signal phase delay which varies with motor speed. This delay must be compensated for in providing the sensorless signal which is proper to the rotor position. A solution for this phase delay compensation, based on a simple analog and digital circuit, is proposed in this paper.     

An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.     

Characterization of single-sided gate-to-drain non-overlapped implantation nMOSFETs for multi-functional non-volatile memory applications

Novel single-sided non-overlapped implantation (SNOI) nMOSFETs are characterized for their capability of multiple programmable memory functions. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using a pure logic processing. To function as mask ROMs, they can be mask-coded with the source drain extension (SDE) implantation. They can also be used as EEPROM devices by trapping charges in the side-wall nitride spacers. Furthermore, SNOI devices can be used as antifuses by introducing the punch-through stress at the drain side. The SNOI devices were successfully demonstrated for antifuse operations with an extremely high program/initial readout current ratio exceeding 10⁹ and a program speed as high as 1 μs. These novel SNOI devices not only provide non-volatile memory solutions in standard CMOS processing but also give a flexible choice among mask ROM, antifuse and EEPROM functions.     

An approach to sequential circuit diagnosis based on formal verification techniques

This article deals with the generation of exact diagnostic trees for real-size synchronous sequential circuits. Starting from existing detection-oriented test patterns, a modified fault simulator is used for assessing their diagnostic power, which, in general, is not satisfactory. A diagnostic procedure for improving it is described that successfully exploits symbolic FSM equivalence proof algorithms. In order to resort to costly techniques, such as product machine traversal, only when really needed, special checks are performed to verify combinational identity and identity on reachable states. As all faults are attributed to theirequivalence class, a complete and exact diagnostic tree can be built. Experimental results on ISCAS'89 circuits show the feasibility of the approach and support the claim that, for the first time, diagnosing real-world synchronous sequential circuits has become feasible.     

An active clamp circuit for voltage regulation module (VRM)applications

This paper discusses the design, fabrication, and testing of a CMOS active clamp circuit, The active clamp is a linear voltage regulator, with a voltage deadband to allow for voltage ripple, that is designed to operate in parallel with a switchmode voltage regulator. Its specific function is to sink or source large transient currents to microprocessor loads, thus allowing operation with very small output capacitance. Laboratory tests on a prototype IC exhibit stable behavior with negligible overshoot with only 47 microfarads of output capacitance with loads of about nine amperes. Output impedances of 2-3 mΩ are achieved     

星载单粒子锁定检测恢复电路设计与实现

星载产品中CMOS器件受单粒子影响发生锁定现象。未避免器件发生单粒子锁定而烧毁,设计实现了星载单粒子锁定检测恢复电路。电路由电流检测放大电路、ADC采集电路、MOSFET开关电路和锁定判断处理电路组成。电路有效解决了大电流、不同器件、不同工作状态下抗单粒子锁定。     

Integrated-optical circuit for fibre gyroscope applications

An integrated-optic chip containing two acousto-optic frequency shifters and a TE-pass polariser is presented. All the elements needed for a fibre-optic gyroscope using the frequency-shift method are realised on one LiNbO₃ chip