Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 $mu {hbox {m}} times,55 mu{hbox {m}}$, uses decoupling capacitance to sense noise and inject a proportional current into $V _{rm SS}$ as a method of reduction. A chip has been designed and fabricated using TSMC's 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%.      

On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit

On-chip resonant supply noise in the mid-frequency range (i.e., 50–300 MHz) has been identified as the dominant supply noise component in modern microprocessors. To overcome the limited efficiency of conventional decoupling capacitors in reducing the resonant supply noise, this paper proposes a low-power digital switched decoupling capacitor circuit. By adaptively switching the connectivity of decaps according to the measured supply noise, the amount of charge provided by the decaps is dramatically boosted leading to an increased damping of the on-chip supply network. Analysis on the charge transfer during the switching events shows a 6-13X boost of effective decap value. Simulations verify the enhanced noise decoupling performance as well as the effective suppression of the first-droop noise. A 0.13 $ mu$m test chip including an on-chip resonance generation circuit and on-chip supply noise sensors was built to demonstrate the proposed switched decap circuit. Measurements confirm an 11X boost in effective decap value and a 9.8 dB suppression in supply noise using the proposed circuit. Compared with previous analog techniques, the proposed digital implementation achieves a 91% reduction in quiescent power consumption with improved tolerance to process-voltage-temperature (PVT) variation and tuning capability for obtaining the optimal switching threshold.      

On-Die Power Supply Noise Measurement Techniques

This paper presents techniques for characterizing wide-band on-chip power supply noise using only two on-chip low-throughput samplers. The properties of supply noise and their associated measurement techniques are reviewed to show how this can be achieved. An initial design of the samplers uses high-resolution VCO-based analog-to-digital converters, and experimental results from a test-chip verify the efficacy of the measurement techniques. To enable simple sampler designs to be used even in aggressively scaled process technologies, measurement systems based on dithered low-resolution samplers are also developed and experimentally characterized.      

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-$mu$ m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11$times$ boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.      

面向SoC任务分配的应用程序存储需求量分析方法

通过分析应用程序的存储需求量,辅助片上系统(System-on-Chip, SoC)任务分配进行数据存储与传输优化,是改善SoC性能的途径之一.目前,存储需求量分析方法的分析粒度单一、速度缓慢,不利于进行多粒度任务分配空间的高效探索.本文面向SoC任务分配,提出一种多粒度、快速存储需求量分析方法.该方法可进行多粒度的存储需求量分析,并针对多媒体程序,引入数组数据域划分技巧,大幅度减少了存储需求量的分析时间.     

Design and Validation of a Power Supply Noise Reduction Technique

For the high-performance microprocessors with high-bandwidth I/O, the power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high-quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). In this paper, we will present two implementations of an approach of using on-die resistors in series with the package capacitance to dampen the high-frequency noise. We will show by validation on the 90-nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings. The results of several validation experiments, including the measurement of noise and impedance of the I/O power delivery, and the post-layout simulation will also be presented.     

Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs

Nanometer-scale VLSI design demands reliable on-chip power/ground (P/G) supply. Decoupling capacitors effectively reduce P/G supply fluctuation at the cost of leakage increase and yield loss. Existing P/G supply network decoupling capacitor insertion techniques are based on sensitivity analysis and greedy optimization. In this paper, we propose a semidefinite program and a linear program for minimum decoupling capacitor insertion in a P/G supply network, which are global optimizations with theoretically guaranteed supply voltage degradation bounds. We also propose scalability improvement schemes which enable application of the proposed semidefinite and linear programs to practical industry designs. Our experimental results on industry designs verify that the proposed semidefinite program guarantees supply voltage degradation bound for all possible supply current sources, while the proposed linear program achieves the most accurate supply voltage degradation control for a given set of supply current sources.     

Power Reduction Techniques for LDPC Decoders

This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low- voltage and low-power operation. First, a highly-parallel decoder architecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. We report on a bit-serial fully-parallel LDPC decoder fabricated in a 0.13-$mu{hbox{m}}$ CMOS process and show how the above techniques affect the power consumption. With early termination, the prototype is capable of decoding with 10.4 pJ/bit/iteration, while performing within 3 dB of the Shannon limit at a BER of 10$^{-5}$ and with 3.3 Gb/s total throughput. If operated from a 0.6 V supply, the energy consumption can be further reduced to 2.7 pJ/bit/iteration while maintaining a total throughput of 648 Mb/s, due to the highly-parallel architecture. To demonstrate the applicability of the proposed architecture for longer codes, we also report on a bit-serial fully-parallel decoder for the (2048, 1723) LDPC code in 10GBase-T standard synthesized with a 90-nm CMOS library.      

Clock Buffer Polarity Assignment for Power Noise Reduction

Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively.      

全双工中继网络的功率分配优化

针对全双工(FD)放大转发中继系统中自干扰造成的符号错误率(SER)性能门限问题,提出了FD放大转发中继系统功率分配优化方案。在考虑自干扰存在的环境下,对系统模型进行了数学分析,推导了中断概率和SER的表达式,制定了基于最小SER准则的优化问题,求出了次优的功率分配比。利用Matlab工具对FD放大转发中继系统SER进行了仿真,证明了该功率分配优化方案的有效性。     

Power Reduction Techniques in Megabit DRAM's

Power dissipation in dynamic random-access memories (DRAM's) is described. Power reduction techniques are summarized and a comparison is made of NMOS and CMOS for individual circuits focusing on power dissipation for full- V/sub cc/ precharge and half- V/sub cc/ precharge, decoder, and clock generator. These results are then applied to actual 1-Mbit chips. The CMOS approach with a half-V/sub cc/ precharge is found to result in a power dissipation of just half that for NMOS, which is, verified through experiments on 1-Mbit CMOS and NMOS chips. Furthermore, from estimating power dissipation for DRAM chips larger than 1 Mbit, it is thought that the critical point for power-supply transition from the existing 5 V is around the 16-Mbit level.     

高能效系统的功耗优化技术

本本将叙述了各种系统选择方案及其对系统功耗的影响，全面介绍了处理器电源管理功能，并讨论总系统功耗的一些重要促进因素。本文网络版地址：http：//www.eepw.com.cn/article/164395.htm     

开关稳压电源用铝电解电容器的失效机理

概述了开关稳压电源用铝电解电容器的工作状态和失效模式，着重讨论了开关稳压电源用铝电解电容器的开路失效和击穿失效机理。     

IDMA系统中基于序列叠加信道估计的功率分配方法

本文在序列叠加信道估计研究的基础上,以交织多址接入系统为模型,利用导频训练序列与信息序列不相关的特性在接收端估计出信道状态信息,并采用最大化有效信噪比的方法给出了训练序列与信息序列的最优功率分配策略.此外,本文讨论了不同统计特性的训练序列对信道估计性能的影响以及估计误差对信道容量的影响,通过仿真研究验证了相关的理论分析,并说明了本文功率分配算法较其它分配策略更有利于提高系统性能.     

铝电解电容在开关电源中的可靠性设计

首先,以BUCK电路为例介绍了开关电源的工作原理;然后,分析了铝电解电容在开关电源中的用途和铝电解电容的特点;最后,在分析铝电解电容的等效电路模型和性能退化的原因和过程的基础上,研究了铝电解电容的热设计和振动因素对于开关电源的可靠性的影响.     

薄膜电容在雷达发射电源中的应用

首先,分析了雷达发射电源输入整流滤波电路的特点;然后,对比分析了铝电解电容与薄膜电容在发射电源输入整流滤波电路中应用的优缺点;最后,通过实验对比了两种电容器在电路中的性能参数。实验部分通过完全替代和部分替代两种方式研究了薄膜电容替换铝电解电容后对发射电源输入整流滤波电路的影响,并分析了这两种方案与传统的铝电解电容的优缺点。实验结果表明:在发射电源输入整流滤波电路中,相比于铝电解电容,薄膜电容具有耐高压、损耗小、寿命长等特点。     

信噪比时变情况下的自适应时延估计方法

本文介绍了一种自适应时延估计的改进方法，此方法用于在信噪比时变情况下，对空间上分离的两个传感器所接收的带限信号的时延估计。它的优点在于：当信噪比变化或未知时，它能对时延的变化随时做出估计。文中给出了此方法的估计精度和收敛特性。     

CMOS集成电路的功耗优化和低功耗设计技术

总结了当前已发展出的各个层次的CMOS低功耗设计技术和低功耗设计方法学的研究进展.重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术.     

基于最大电源噪声门级模型的遗传算法电源噪声估计

提出一种能够综合考虑IR drop和di/dt噪声的门级电路模型.实验表明,利用这种模型进行电源噪声估计,可以比传统模型提高5.3%的精度,同时运算时间降低10.7%.根据输入信号对最大电源噪声的影响,还提出了关键输入信号模型.实验表明,在进行电源噪声估计中,基于这些模型的遗传算法,能够比传统的遗传算法提高最多19.0%的精度,并且收敛更加迅速.     

基于最大电源噪声门级模型的遗传算法电源噪声估计

提出一种能够综合考虑IR drop和di/dt噪声的门级电路模型.实验表明,利用这种模型进行电源噪声估计,可以比传统模型提高5.3%的精度,同时运算时间降低10.7%.根据输入信号对最大电源噪声的影响,还提出了关键输入信号模型.实验表明,在进行电源噪声估计中,基于这些模型的遗传算法,能够比传统的遗传算法提高最多19.0%的精度,并且收敛更加迅速.