Microscopic simulation of RF noise in junctionless nanowire transistors

A deterministic solver for the analysis of microscopic noise and small-signal fluctuations in junctionless nanowire field-effect transistors is presented, which is based on a self-consistent and simultaneous solution of the Poisson/Schrödinger/Boltzmann equations. It is verified that the numerical framework fulfills the vital properties of reciprocity and passivity in the small-signal sense, and yields Johnson–Nyquist noise under equilibrium conditions. Key figures such as the cutoff frequency, drain excess noise factor, the Fano factor, and gate/drain correlation coefficient are presented at various bias conditions. In this work we show that similar to the inversion-mode MOSFETs, the gate and drain current noises mainly stem from the warm electrons at the source side, whereas the hot electrons do not have a significant contribution. Also, our results show that the device behaves similar to long-channel FETs in terms of its excess noise even for a channel length of 10 nm, due to the strong control of its electrostatics by the all-around gate.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Journal of Computational Electronics - This work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical...     

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory

Continued scaling of transistors into the nanoscale regime has led to large device-to-device variation in transistor characteristics. These variations reflect differences in substrate doping, channel length, interface and/or oxide defects, etc. among various transistors. In this paper, we develop a theory for the statistical distribution of threshold voltage degradation (ΔV _T ) due to the Negative Bias Temperature Instability (NBTI). First, we model the time dynamics of interface defects within the Reaction-Diffusion (R-D) framework and calculate the statistics of interface defect using Markov Chain Monte-Carlo method. We show that the generation and annealing of interface defects are strongly correlated and that the statistics of interface defect at a given stress time (N _IT @t _STS ) follows a skew-normal distribution. Second, we explore the differential effect of the spatial distribution of interface defects in nanoscale transistors pre-populated with a discrete number of randomly placed substrate dopants. We model the effect of spatial distribution of defects using a percolative network and demonstrate that the distribution of threshold voltage degradation for a single additional interface defect, i.e., ΔV _T @ΔN _IT =1, is exponential, with a fraction of transistors having ΔV _T ∼0. Finally, we obtain the statistics of ΔV _T @t _STS by convolving the statistics of N _IT @t _STS with that of ΔV _T @ΔN _IT =1. The resultant statistics of ΔV _T @t _STS compares favorably with a broad range of experiments reported in the NBTI literature.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance

Over the years, the approach of cylindrical gate MOSFETs has attracted several research initiatives due to the very inherent benefit of the cylindrical geometry over other conventional planar structures. Nowadays, the present boon in the research field of nanoscale device physics is attributed to a large extent by the development of junctionless devices. In our current research endeavor, we have for the first time proposed a new idea by incorporating the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate into a junctionless cylindrical gate MOS structure, thereby presenting a new device structure, a junctionless work function engineered gate cylindrical gate MOSFET (JL WFEG CG MOSFET). We have presented a rigorous analytical modeling of the proposed JL WFEG CG MOS structure by solving the two dimensional Poisson’s equation in cylindrical co-ordinates. Based on this analytical modeling, an overall performance comparison of the proposed JL WFEG CG MOS and normal JL CG MOS structure has been investigated in order to testify the improved performance of the proposed JL WFEG CG structure over its normal JL CG equivalent in terms of reduced short channel effects, threshold voltage roll off, drain induced barrier lowering and superior current driving capability. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

Quantum ballistic transport in the junctionless nanowire pinch-off field effect transistor

In this work we investigate quantum ballistic transport in ultrasmall junctionless and inversion mode semiconducting nanowire transistors within the framework of the self-consistent Schrödinger-Poisson problem. The quantum transmitting boundary method is used to generate open boundary conditions between the active region and the electron reservoirs. We adopt a subband decomposition approach to make the problem numerically tractable and make a comparison of four different numerical approaches to solve the self-consistent Schrödinger-Poisson problem. Finally we discuss the IV-characteristics for small (r≤5 nm) GaAs nanowire transistors. The novel junctionless pinch-off FET or junctionless nanowire transistor is extensively compared with the gate-all-around (GAA) nanowire MOSFET.     

Characterization of hot carrier degradation within the gate oxide of short channel MOSFET's

Ohne Zusammenfassung

---

Characterization of hot carrier degradation within the gate oxide of short channel MOSFET's

     

Computers and art: a dancer's perspective

When we speak of the role of computers in art, we could be referring to quite different things: art that is concerned with computers, or art that is merely created using computers. The computer's application to dance may indeed be viable, but as the influence of computers continues to grow, changing the world in ways we can hardly imagine today, it becomes a task for all of us-though perhaps especially for artists-to look very carefully at these strange “tool-like” things, to turn them slowly in our hands, heads tilted     

Effect of process parameter variation on f t in n-type junctionless FETs

In this paper we have studied the effect of fin width (W), fin height (H), gate oxide thickness (T _ox), gate length (L _g) and doping (N _d) values variations on unity gain cut-off frequency (f _t) in Junctionless FET by performing extensive Technology CAD (TCAD) simulations. The parasitic series resistance decreases as fin width, fin height and doping increases while the total input capacitance (C _gg) increases. Except the higher T _ox with elevated doping values, the device is in g _m dominated region resulting in increased f _t as fin width, fin height and doping values increase.     

Amplifier analysis: a tradeoff perspective

Conventional treatment of amplifiers emphasizes relationships between specifications and circuit parameters and gives only marginal importance to relationships among the specification themselves. With a view that an understanding of tradeoffs among specifications is very important from the design perspective, a representation of amplifier results is presented that explicitly highlights these relationships. Results are presented for some commonly used bipolar and metal-oxide-semiconductor field-effect transistor (MOSFET) amplifier topologies.     

Nonlinear control in rolling mills: a new perspective

This paper is concerned with the application of modern nonlinear control techniques to the thickness control in rolling mills. It turns out that the performance of the closed loop can be significantly improved by taking into account the essential nonlinearities of the plant to be controlled already in the controller design. These nonlinear control strategies totally differ from the common approach of linearizing the nonlinear system around a nominal operating point, because they are not limited to a more or less small neighborhood of the operating point, but are valid all over the operating range. Practically, these nonlinear control concepts are a possible answer to the trend of modern rolling mills toward tighter thickness tolerances, thinner final strip thicknesses, faster production rates and shorter off-gauge lengths. However, a straightforward application of the well established nonlinear control theory does not always lead to a control concept that is practically feasible. It is rather unavoidable to consider all the special features and properties of the plant. By means of the gap control of a mill stand with a hydraulic positioning system, the authors show in detail the advantages of a nonlinear control approach. Finally, simulation and measurement results demonstrate the feasibility and the excellent performance of the proposed design