Some general properties of power electronic conversion networks

Contents The conversion capability of power semiconductor devices used in power electronic conversion networks is explained. A general power electronic conversion network is defined and the general power relationships relating the real power transferred through the conversion network with the real power transformed by means of conversion devices are derived. Starting from the general power relationships, the poperties of power electronic conversion networks for rectification, inversion, frequency conversion and d.c. conversion are explained. All properties are derived disregarding the internal structure of particular conversion networks.

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Einige allgemeine Eigenschaften der Leistungselektronik-Umformernetze

Übersicht Die Umformungsfähigkeit der in Leistungselektronik-Umformernetzen eingesetzten Halbleiterbauelemente wird erläutert. Ein allgemeines Leistungselektronik-Umformernetz wird definiert. Die allgemeinen Leistungsbeziehungen werden ausgeführt, welche die durch das Umformernetz übertragene Wirkleistung mit der mittels Umformerbauelemente umgeformten Wirkleistung in Zussammenhang bringen. Ausgehend von den allgemeinen Leistungsbeziehungen werden die Eigenschaften der Leistungselektronik-Umformernetze für Gleichrichtung, Wechselrichtung, Frequenzumformung und Gleichstromumformung erläutert. Alle Eigenschaften werden ohne Berücksichtigung der inneren Struktur einzelner Leistungsumformernetze abgeleitet.

     

Microwave surfing. Wireless networks: an electronic battlefield?

Dealing with covert surveillance and jamming may seem business as usual to microwave engineers working in the defense sector, but the same issues will appear rather remote to their colleagues in the wireless business. However, as the reports given suggest, wireless network designers may need to use their own countermeasures to avoid being ambushed on the electronic battlefield     

Research on power electronic transformer applied in AC/DC hybrid distribution networks

The AC/DC hybrid distribution network is one of the trends in distribution network development, which poses great challenges to the traditional distribution transformer. In this paper, a new topology suitable for AC/DC hybrid distribution network is put forward according to the demands of power grid, with advantages of accepting DG and DC loads, while clearing DC fault by blocking the clamping double sub-module(CDSM) of input stage. Then, this paper shows the typical structure of AC/DC distribution network that is hand in hand. Based on the new topology, this paper designs the control and modulation strategies of each stage, where the outer loop controller of input stage is emphasized for its twocontrol mode. At last, the rationality of new topology and the validity of control strategies are verified by the steady and dynamic state simulation. At the same time, the simulation results highlight the role of PET in energy regulation.     

用神经网络对风力发电中电力电子故障分析

随着风能资源的利用水平不断提高,风力发电系统中的电力电子装置使用也越来越多,其工作可靠性要求也越来越高。风力发电装置多位于野外,为减轻检修人员的工作负担,对风机运行中远方检测到的大量数据进行快速而有效的可视化分类及故障状态粗略判断,引入了一种用单层前向神经网络来对数据进行快速分类绘制故障非故障分界线的方法。通过该方法能够很好地根据实时数据判断风机电力电子装置的故障。     

The voltage distortion in low-voltage networks caused by compact fluorescent lamps with electronic gear

Commonly used compact fluorescent lamps (CFLs) with electronic gear are characterized by extremely distorted current, with total harmonic distortion (THD) usually exceeding 100%. That is why they cause a significant voltage distortion in electrical installations. The principal goal of this research was to determine their maximum permissible share in the total load installed for commercial customers, at which voltage distortion is still acceptable (according to international standards). An analysis regarding a low-voltage electrical installation of a hotel, representing a typical commercial customer, showed that maximum permissible share should not exceed 10%. As this maximum permissible share could restrict the installment of the intended quantity of CFLs, the costs of two possible solutions for this problem – the use of filters or a new generation of CFLs with a high power factor – are compared.     

Analytic transient solution of SCFL logic gates

In this paper we propose the analytical solution of switching transients for SCFL logic gates. The analysis of an SCFL logic gate is carried out without linearization and can be brought back to multiple analyses of a basic cell, given by a differential pair with switching input voltages and a variable tail current, to take the effect of series‐gating into account. The differential equation for this cell is a Riccati equation, if a quadratic current–voltage relationship is used for the transistors, and it can be solved by the infinite power series method, in case of polynomial input signals. An algorithm is proposed to analyse the full transient of a complex SCFL gate. This provides a closed form expression for transient signals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time‐domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AH technology, and a good agreement between the proposed model and SPICE simulations using complex device models is obtained. Copyright © 2005 John Wiley & Sons, Ltd.     

Modelling of source‐coupled logic gates

In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single‐pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed. The expressions obtained are simple enough to be used for pencil‐and‐paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology. The model has been validated by comparison with extensive simulations using a 0.35‐µm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil‐and‐paper evaluations and for computer‐based timing analysis of complex SCL circuits. Copyright © 2002 John Wiley & Sons, Ltd.     

A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology

Quantum dot cellular automata (QCA) with the characteristics such as low energy dissipation and high density is a suitable alternative technology to CMOS technology. Arithmetic logic unit (ALU) is one of the most important critical components of a microprocessor, and it is the core component of central processing unit (CPU). In this work, a novel reversible ALU in QCA nanotechnology is proposed. The reversible ALU contains three Ferdkin gates and one HNG gate. The proposed structure needs one constant input and generates only one garbage output. The proposed circuit does not need any rotated cells and only uses one layer that improves the manufacturability of the design interestingly. This circuit can perform 20 operations such as AND, OR, XOR, XNOR, COPY, addition, and increment. Our design contains only 480 cells and 12 majority voters and requires 15 clock phases. The proposed structures are simulated using QCADesigner version 2.0.3. The reversible ALU, despite a 25% increase in operations, has a 28% improvement in cell numbers and a 6% improvement in delay.     

A thymine-based molecular structure to design logic gates and memory devices

Journal of Computational Electronics - A computational study is carried out on thymine using the two-probe method. A thymine molecule with thiol anchors is sandwiched between two gold...     

水轮机导叶“先快后慢”关闭规律适用性研究

导叶关闭规律的优化是水电站调节保证计算的重要研究内容，采用合理的关闭规律降低水锤压强与限制机组转速升高，是一种经济有效的措施。本文基于某实际水电站，建立了引水发电系统过渡过程数学模型，模拟了电站控制工况下的过渡过程，研究了导叶关闭规律对输水系统的影响，结论表明先快后慢的导叶关闭规律适用于水锤极值和转速极值出现在不同工况的水电站。先快后慢分段关闭规律解决了该类电站一段直线关闭无法满足调保计算要求的问题。     

事故闸门爬行振动数值反演与影响因素分析北大核心CSCD

为研究事故闸门爬行振动特征和影响因素,基于原型闸门闭门过程中的振动响应,分析闸门振动特性,确定振动类型。通过类比摩擦学中的干摩擦自激振动,建立事故闸门闭门过程中的振动数值模型,反演闸门振动响应过程,探究闭门速度、闸门质量和摩擦系数等因素对闸门振动的影响。结果表明,事故闸门爬行振动是一种特殊的自激振动,其振幅随闸门开度减小而逐渐增大。闸门与轨道间的动静摩擦转化是引起爬行振动的最根本原因,振动响应强度与面板水推力和动静摩擦系数差值成正比。闭门速度对振动影响较大,存在临界闭门速度,可用于区别闸门是否出现爬振,且临界闭门速度与静摩擦系数有关。闸门质量影响钢绳索初始变形量和闭门时间,进而对爬行振动产生影响。闸门下落闭门,钢绳索长度增加,系统刚度减小,导致振幅和周期增大。     

基于模型优化与TR方法的水工弧形闸门损伤识别

针对水工弧形闸门的安全监测问题,基于结构动力模型优化技术提出水工闸门损伤识别与健康诊断一种解决方案。该方案将水工钢结构的损伤识别和健康诊断问题首先转化为一种非线性约束优化问题,通过建立带边界约束的非线性最小二乘目标函数,极小化结构实测模态与理论计算模态之间的误差,采用具有更强鲁棒性和可靠性的信赖域（TR）方法求解该优化问题,达到识别结构损伤位置及其程度的目的,从而为水工钢闸门的健康诊断提供技术措施和方案。最后通过一个水工弧形闸门模型的损伤识别数值仿真和试验研究,证明了该方案应用于水工钢闸门结构损伤识别与健康诊断的可行性和有效性。     

Simple and accurate modeling of the output transition time in nanometer CMOS gates

In this paper, a model of the output transition time on nanometer CMOS gates is proposed. The development of this model follows the general approach used by Auvergne in (IEE Electron. Lett. 2002; 38 (4):175–177, IEEE Trans. Circuits Systems—part I 2000; 47 (9):1362–1369, IEEE Proc. ISCAS 2001; 5 :363–366, IEEE Trans. Computer‐Aided Design Integr. Circuits Systems 2002; 21 (11):1352–1363), which separately models the output transition time under fast and slow inputs. The proposed model is based on a combined transient and DC circuit analysis, and requires a few simulations. This approach allows for strongly reducing the number of required parameters and simulations compared with other models proposed in the literature. The analytical model proposed is very simple and has a clear physical meaning, thereby allowing an efficient implementation in CAD tools performing timing analysis, as well as an easy scalability through different processes and technology generations. Spectre simulations on a 65 nm CMOS technology and the 45, 32, 22 nm Berkeley Predictive Technology Models (BPTM) [Berkeley Predictive Technology Model (BPTM). ONLINE@11/25/2008: http://www.eas.asu.edu/～ptm/ ] show that the model accuracy is the same as the state‐of‐the‐art models, with an average error of only 4%. Comparison with currently used table‐based models showed also a significant reduction in the CPU time needed to simulate and characterize CMOS logic gates. Copyright © 2009 John Wiley & Sons, Ltd.     

Modelling and design considerations on CML gates under high‐current effects

In this paper, the effect of the transit time degradation of bipolar transistors on the power‐delay trade‐off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high‐speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18 (9):1369–1375; Model and Design of Bipolar and MOS Current—Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed‐form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power‐delay trade‐off by considering the effect of the transit time degradation in high‐speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil‐and‐paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20‐GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd.     

节制闸对分水口处渠道水力响应的影响及敏感性研究

节制闸的运用是渠道运行控制的主要手段,是影响渠道水力响应的重要因素。本文以南水北调东线小运河干渠为研究对象,选取分水口处水位下降速率、水位最大降幅和水位过渡时间作为表征渠道水力响应的指标,在渠道分水口取水流量增大的情况下,研究节制闸调节对分水口处渠道水力响应的影响规律。在此基础上分析分水口处渠道水力响应对节制闸调节的敏感性,提出基于节制闸调节的渠道水力响应敏感性指标,该指标能定量的反应闸门调节幅度、节制闸与分水口间距对渠道水力响应的影响程度。研究表明,分水口处渠道水力响应对闸门调节幅度的影响较为敏感,对节制闸与分水口间距影响的敏感程度次之。     

蜀河水电站弧形闸门原型观测试验研究

随着我国水利水电工程技术的发展,越来越多的大尺寸弧形闸门投入使用,对弧形闸门的原型观测试验技术手段提出了更高的要求。在现阶段国内外尚无水工金属结构设备原型观测专项技术标准状况下,本文针对弧形闸门的工作特点,提出了弧形闸门原型观测试验整体技术方案。并以蜀河水电站泄洪闸2#弧形闸门原型观测试验为例,通过采用先进的测量仪器和数据分析技术,对弧形闸门的结构应力、位移、动力特性、振动响应、启闭力等各项工作特性参数进行了综合评价和分析。发现了支臂侧向作用面上承受较大弯矩、下泄水流的动水荷载与弧形闸门和闸墩的低频区已形成不利组合、启门瞬间液压启闭机的启门力超出启闭机容量等弧形闸门的运行安全隐患,对确保工程安全具有一定的参考价值。     

浅谈电子设备类和电子器件类的静电测试

静电放电是一个复杂多变的随机过程,同时静电放电有许多不同的放电形式,产生静电放电的静电源多种多样。根据不同场合静电放电的主要特点可以建立相应的静电放电模型来模拟静电放电的主要特征,同时指定相应的测试方法,静电测试分为电子设备级(系统级)静电测试和电子器件级(元件级)静电测试,其所用的测试方法和测试仪器都不相同。     

网络化电测仪表

提出了电测仪表要向网络化发展，应利用当今互联网的丰富资源，让各种测控仪表能方便地挂到互联网上,组成一个庞大的远程自动测控系统。中介绍了用单片机设计的微型网站，有自己的网址和主页，可以直接连入互联网，进行异地实时测控，是实现网络化电测仪表较为经济实用的设计方案。中还给出了两个应用实例。