Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of \(0.02\,\upmu \hbox {m}^{2}\) and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.     

A novel QCA implementation of MUX-based universal shift register

QCA (Quantum-dot Cellular Automata) is an alternative technology for CMOS that has a low power consumption and high density. QCA extensively supports the new plans in the field of nanotechnology. Applications of QCA technology as an alternative method for CMOS technology in nano-scale have a hopeful future. This paper presents the successful design, implementation and simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexer with the minimum area as compared to the previous models in QCA technology. In this paper, by means of 4 to 1 multiplexers including D-Flip Flop (D-FF) structure in QCA, we present an 8-bit universal shift register. The structure of the 8-bit universal register is extendable to 16-bit, 32-bit and etc. In this paper, the successful simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexers, including D-FF and finally 8-bit universal register structure in QCADesigner is provided. The multiplexers and D-FF presented in this paper have the minimum complexity, area and delay compared to the previous models. In this paper, the implementation of 8-bit universal shift register, by means of 4 to 1 multiplexers and D-FF are presented in QCA technique which have the minimum complexity and delay. In the proposed design of the 8-bit universal shift register, the faults are likely to occur at 2 to 1 multiplexers and D-FF. In this article, 2 to 1 multiplexers and D-FF are investigated from the cell missing and possible defects. Considering the pipeline being the virtue of QCA, the 8-bit universal shift register has a high speed function. This 8-bit universal shift register may be used in the high speed processors as well as cryptography circuits.     

A symmetric quantum-dot cellular automata design for 5-input majority gate

By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.     

Four innovative calibration algorithms for capacitive mismatch in 18-bit redundant split SAR ADC

Four calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog-to-digital converter (ADC). An 18-bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte-Carlo runs with a standard deviation of 0.1% (σ₀/C₀ = 0.001 ). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64-dB enhancement of spurious-free dynamic range (SFDR) and a 3.33-bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re-exchanging method I (SREI) show that a 21.64-dB enhancement of SFDR and a 3.34-bit improvement of ENOB have achieved, respectively     

Design and simulation of modular 2n to 1 quantum‐dot cellular automata (QCA) multiplexers

In this paper a novel design of a quantum‐dot cellular automata (QCA) 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed, which can be used to design 2ⁿ to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability. Copyright © 2009 John Wiley & Sons, Ltd.     

High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

In this paper, high-throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2ⁿ, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works.     

高性能CMOS全加器设计

全加器是数字信号处理器、微处理器中的重要单元,它不仅能完成加法,还能参与减法、乘法、除法等运算,所以,提高全加器性能具有重要意义.本文分析了两种普通全加器,运用布尔代数对全加器和函数、进位函数进行全面处理,提取了和函数、进位函数优化函数式.根据最优化函数式,设计了高性能CMOS管级全加器单元电路.这种CMOS全加器电路与常用CMOS全加器电路相比,电路结构简单、芯片面积小、电路传输延迟时间小、运算速度快.     

Design of low power approximate floating‐point adders

Due to the increasing demands for more power in data intensive computing, low power design methodologies play a very important role in these systems. For noncritical data, the approximate computing that significantly reduces the power can be used. In this paper, an approximate floating‐point adder is proposed by designing an inexact mantissa adder and exponent subtractor. The results indicate that the power consumption and delay of the proposed approximate floating‐point adder have been decreased by 37% and 62% compared with the IEEE‐754 single‐precision floating‐point (FP) adder. Furthermore, compared with a state‐of‐the‐art inexact floating‐point adder, the proposed method provides an improvement of 7% and 21% in terms of the power consumption and delay. In addition, the proposed floating‐point adder has been investigated in terms of error, and the mean error of the proposed floating‐point adder at worst is about 55% less than that of another approximate floating‐point adder considered in this work. High dynamic range (HDR) images are processed using the proposed approximate floating‐point adders to show the performance of the proposed adder. The results show that, on average, peak signal‐to‐noise ratio increased by 9.6 and 18.64 dB, which may be achieved by utilizing the proposed floating‐point adder.     

Architecture for an external input into a molecular QCA circuit

A simple architecture for data input into a molecular quantum-dot cellular automata (QCA) circuit from an external CMOS circuit is proposed. A “T”-shaped interconnect, utilizing fixed-polarization cells to provide the desired polarization, is controlled via external electrodes connected to a standard CMOS input driver. The applied input signal is used to gate either the propagation of a fixed polarization, P=+1, or that of the complementary fixed polarization, P=−1, into the QCA circuit. The architecture utilizes the field-driven clocking scheme proposed in recent literature to achieve transduction between applied input voltage and a molecular configuration. The system is modelled using the coherence vector formalism with a three-state basis and simulated using the QCADesigner simulation tool.     

An improved decision feedback equalization using a priori information

This paper addresses the exhaustive computational complexity of the maximum‐a‐posteriori equalizer and the inefficiency of the conventional decision feedback equalizer (DFE) algorithm in iterative equalization, especially when the higher‐level modulation is used with severely distorted Inter Symbol Interference channels. The new method proposed here improves the bit error rate (BER) performance by computing the extra metric r_n+1 using the feedback symbols from previous iteration and combining it with a priori information of the symbols. After each iteration, the hard‐detected symbols are saved in the memory as a priori data for next iteration. We verified the proposed algorithm for Binary Phase Shift Keying and 8‐phase shift keying modulation. The promising simulation results show that the BER performance given by the proposed low complexity DFE algorithm improved dramatically throughout the iterations when the conventional DFE has only insignificant improvement in the process of iterative equalization. Copyright © 2009 John Wiley & Sons, Ltd.     

QCA技术在递归盒式滤波器中的应用

量子点元胞自动机(quantum dot-cellular automata, QCA)因其延迟时间短、功耗低以及占用面积小等优点被当作代替CMOS的新型技术之一。针对CMOS器件尺寸日益减小导致的高功耗和电容寄生及串扰问题,本文首次利用QCA技术构建了一种递归盒式滤波器。其中,提出了一种全新的QCA全加器,较已提出的QCA全加器减少了55%的电路面积;少使用了56.7%的元胞数;量子成本也降低了10%以上。并以此为基础设计了一种高效的行波进位加法器(ripple carry adder, RCA)以及一种高效的进位选择加法器(carry select adder, CSA)来构成盒式滤波器的加法单元。以此构建的盒式滤波器较一般QCA盒式滤波器节省了32.6%的硬件资源;减少20%的电路运行时间;减少了48.7%的功耗。并使用QCA Designer仿真,结果表明,本设计完全可以代替实现传统的盒式滤波器功能,并在效率、功耗、电路面积、资源占用方面均有显著降低。     

An analytical model for a TFET with an n-doped channel operating in accumulation and inversion modes

The tunnel field-effect transistor (TFET) is an ambipolar device that conducts current with the channel in both accumulation and inversion modes. Analytical expressions for the channel potential and current in a TFET with an n-doped channel when operating in the accumulation and inversion modes are proposed herein. The potential model is derived by solving the two-dimensional (2D) Poisson equation using the superposition principle while considering the charges present in the channel due to electron or hole accumulation along with the depletion charges. An expression for the tunneling current corresponding to the maximum tunneling probability is also derived. The tunneling current is obtained by analytically calculating the minimum tunneling length in a TFET when operating in the accumulation or inversion mode. The results of the proposed potential model is compared with technology computer-aided design (TCAD) simulations for TFET with various dimensions, revealing good agreement. The potential and current in an n-type TFET (nTFET) obtained using the proposed models are also analyzed.

     

Towards the design of hybrid QCA tiles targeting high fault tolerance

The increasing fabrication cost of CMOS-based computing devices and the ever-approaching limits of their fabrication have led to the search for feasible options with high device density and low power waste. Quantum-dot cellular automata (QCA) is an emerging technology with such potential to match the design target beyond the limits of state-of-the-art CMOS. But nanotechnologies, like QCA are extremely susceptible to various forms of flaws and variations during fabrication at nano scale. Thus, the exploration of ingenious fault tolerant structure around QCA is gaining high importance. This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy. Different QCA logic primitives (majority/minority logic, fanout tiles, etc.) are made using such hybrid cell structure. The functional characterization using the kink energy and the polarization level of such QCA structures under different cell defects have been thoroughly investigated. The results suggest that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %. Also, 100 % fault tolerance can be ascertained if the proposed logic circuit drives the correct output with the application of \(\langle \)001, 011\(\rangle \) as a primitive test vector only. A comparative performance of the proposed logic over existing structure makes it more reliable.     

Simulation-based evaluation of SAR and flip angle homogeneity for five transmit head arrays at 14 T

Introduction

Various research sites are pursuing 14 T MRI systems. However, both local SAR and RF transmit field inhomogeneity will increase. The aim of this simulation study is to investigate the trade-offs between peak local SAR and flip angle uniformity for five transmit coil array designs at 14 T in comparison to 7 T.

Methods

Investigated coil array designs are: 8 dipole antennas (8D), 16 dipole antennas (16D), 8 loop coils (8D), 16 loop coils (16L), 8 dipoles/8 loop coils (8D8L) and for reference 8 dipoles at 7 T. Both RF shimming and k_T-points were investigated by plotting L-curves of peak SAR levels vs flip angle homogeneity.

Results

For RF shimming, the 16L array performs best. For k_T-points, superior flip angle homogeneity is achieved at the expense of more power deposition, and the dipole arrays outperform the loop coil arrays.

Discussion and conclusion

For most arrays and regular imaging, the constraint on head SAR is reached before constraints on peak local SAR are violated. Furthermore, the different drive vectors in k_T-points alleviate strong peaks in local SAR. Flip angle inhomogeneity can be alleviated by k_T-points at the expense of larger power deposition. For k_T-points, the dipole arrays seem to outperform loop coil arrays.

     

A gain/efficiency‐enhanced bidirectional switched‐capacitor DC‐DC converter

A closed‐loop gain/efficiency‐enhanced bidirectional switched‐capacitor converter (BSCC) is proposed by combining an adaptive‐conversion‐ratio (ACR) phase generator and pulse‐width‐modulation (PWM) controller for bidirectional step‐up/down DC‐DC conversion and regulation. For realizing gain‐enhanced, the power part consists of one m_c‐stage cell and one n_c‐stage cell in cascade between low‐voltage (LV) and high‐voltage (HV) sides to boost HV voltage into m_c × n_c times voltage of LV source at most, or convert LV voltage into 1/(m_c × n_c) times voltage of HV source at most. For realizing efficiency‐enhanced, the ACR idea with adapting stage number m, n is built in the phase generator to obtain a suitable step‐up/down gain: m × n or 1/(m × n) (m = 1, 2, …, m_c, n = 1, 2, …, n_c). Further, the output regulation and robustness to source/loading variation can be enhanced by PWM on the LV/HV sides. Some theoretical analysis and control design are included as: modeling, steady‐state analysis, conversion ratio, efficiency, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a BSCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Robust QCA full-adders using an efficient fault-tolerant five-input majority gate

Quantum-dot cellular automata (QCA) is considered as a top candidate for nanoscale technologies with unique features such as very low occupancy and ultralow power consumption. Despite the potential benefits of QCA technology over CMOS technology, QCA circuits are highly prone to defects. Therefore, a demand has risen in designing fault-tolerant circuits. In this research, a novel fault-tolerant five-input majority gate is first suggested, and then it is evaluated by implementing a variety of faults such as cell omission, cell displacement, and extra-cell deposition. The evaluation results reveal that the proposed structure is 100%, 51.85%, and 18.8% fault-tolerant under extra-cell deposition, single-cell omission, and double-cell omission, respectively. Moreover, two single-layer and coplanar fault-tolerant QCA full-adders are offered using the suggested fault-tolerant structure. The stability of the presented single-layer full-adder has also been investigated under single and double cell omission defects. The evaluation outcomes show that the suggested fault-tolerant single-layer full-adder has a high stability in Sum and C_out outputs compared with other full-adders. In order to validate the functionality of the suggested fault-tolerant five-input majority gate, a number of physical investigations are given. The QCADesigner 2.0.3 software has been used to evaluate the simulation results.     

Mixed norm regularized recursive total least squares for group sparse system identification

A mixed l_p,0‐regularized recursive total least squares (RTLS) algorithm is considered for group sparse system identification. Regularized recursive least squares (RLS) has been successfully applied to group sparse system identification; however, the estimation performance in regularized RLS‐based algorithms deteriorates when both input and output are contaminated by noise (the error‐in‐variables problem). We propose an l_p,0‐RTLS algorithm to handle group sparse system identification with errors‐in‐variables. The proposed algorithm is an RLS‐like solution that utilizes l_p,0‐regularization. The proposed algorithm provides excellent performance as well as reduces the required complexity by effective inversion matrix handling. Simulations demonstrate the superiority of the proposed l_p,0‐regularized RTLS for a group sparse system identification setting. Copyright © 2015 John Wiley & Sons, Ltd.