Analysis and modeling of World Wide Web traffic for capacity dimensioning of Internet access lines

A study on traffic characterization of the Internet is essential to design the Internet infrastructure. In this paper, we first characterize WWW (World Wide Web) traffic based on the access log data obtained at four different servers. We find that the document size, the request inter-arrival time and the access frequency of WWW traffic follow heavy-tail distributions. Namely, the document size and the request inter-arrival time follow log-normal distributions, and the access frequency does the Pareto distribution. For the request inter-arrival time, however, an exponential distribution becomes adequate if we are concerned with the busiest hours. Based on our analytic results, we next build an M/G/1/PS queuing model to discuss a design methodology of the Internet access network. The accuracy of our model is validated by comparing with the trace-driven simulation. We also investigate the effect of document caching at the Proxy server on the WWW traffic characteristics. The results show that the traffic volume is actually reduced by the document replacement policies, but the traffic characteristics are not much affected. It suggests that our modeling approach can be applied to the case with document caching, which is demonstrated by simulation experiments.     

Design and implementation of dual processor block with shared external cache memory

The availability of low cost, high performance microprocessors has led to various designs of shared memory multiprocessor systems. As a result, commercial products which are based on shared memory have been proliferated. Such a multiprocessor system is heavily influenced by the structure of memory system and it is not difficult to find that most configurations include local cache memories. The more processors a system carries, the larger local cache memory is needed to maintain the traffic to and from the shared memory at reasonable level. The implementation of local cache memories, however, is not a simple task because of environmental limitations. In particular, the general lack of board space availability presents a formidable problem. A cache memory system usually needs space mostly to support its complex control logic circuits for the cache itself and network interfaces like snooping logic circuits for shared bus. Although packaging can be made denser to reduce system size, there are still multiple processors per board. It requires a more area-efficient cache memory architecture. This paper presents a design of shared cache for dual processor board of bus-based symmetric multiprocessors. The design and implementation issues are described first and then the evaluation and measurement results are discussed. The shared cache proposed in this paper has been determined to be quite area-efficient without the significant loss of throughput and scalability. It has been implemented as a plug-in unit for TICOM, a prevalent commercial multiprocessor system.     

Numerical modeling of the flow field and performance in cyclones of different cone-tip diameters

The effect of the cone tip-diameter on the flow field and performance of cyclone separator was investigated computationally and via mathematical models. Three cyclones with different cone tip diameters were studied using large eddy simulation (LES). The cyclone flow field pattern has been simulated and analyzed with the aid of velocity components and static pressure contour plots. In addition the cyclone collection efficiency based on one-way discrete phase modeling has been investigated. The results obtained demonstrate that LES is a suitable approach for modeling the effect of cyclone dimensions on the flow field and performance. The cone tip-diameter has an insignificant effect on the collection efficiency (the cut-off diameter) and the pressure drop. The simulation results agree well with the published experimental results and the mathematical models trend.