Gate shadowing effect on Ni(Pt)Si abnormal diffusion for sub-45 nm technologies

In the frame of the 40 nm technology node development, Ni(Pt)Si abnormal diffusion, usually called NiSi encroachment is studied through voltage contrast electron beam inspection. A typical mapping is found for 300 mm-Si(1 0 0) wafers which is related to NiPt deposition asymmetry, in active zones, between two transistor gates. This observation is related to “gate shadowing effect”, which induces thinner NiPt thickness and then lower Pt amount at the edge of active zones. TEM analyses of the local NiPt thickness and electrical characterizations as junction leakage permit to determine the minimum of NiPt thickness and/or Pt amount needed to guaranty an adequate NiSi stability.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.     

Ni/Pd/Si固相反应及NiSi热稳定性增强研究

研究了Ni/Pd双层薄膜在硅衬底上的硅化物形成过程.结果表明,加入Pd层后,退火形成Ni1-xPdxSi固熔体,该固熔体比NiSi的热稳定性好,使得NiSi向NiSi2的转变温度升高.加入Pd的量越多,NiSi2的成核温度越高,并用经典成核理论解释了该现象.     

掺Pt对Si(100)上形成的NiSi薄膜应力的影响

利用在线应力测试技术表征了掺入Pt后对镍硅化物薄膜应力性质的影响.通过改变NiSi薄膜中Pt含量以及控制热处理的升温、降温速率实时测量了薄膜应力,发现在Si(100)衬底上生长的纯NiSi薄膜和纯PtSi薄膜的室温应力主要是热应力,且分别为775MPa和1.31GPa,而对于Ni1-xPtxSi合金硅化物薄膜,室温应力则随着Pt含量的增加而逐渐增大.应力随温度变化曲线的分析表明,Ni1-xPtxSi合金硅化物薄膜的应力驰豫温度随Pt含量的增加,从440℃(纯NiSi薄膜)升高到620℃(纯PtSi薄膜).应力驰豫温度的变化影响了最终室温时的应力值.     

掺Pt对Si(100)上形成的NiSi薄膜应力的影响

利用在线应力测试技术表征了掺入Pt后对镍硅化物薄膜应力性质的影响.通过改变NiSi薄膜中Pt含量以及控制热处理的升温、降温速率实时测量了薄膜应力,发现在Si(100)衬底上生长的纯NiSi薄膜和纯PtSi薄膜的室温应力主要是热应力,且分别为775MPa和1.31GPa,而对于Ni1-xPtxSi合金硅化物薄膜,室温应力则随着Pt含量的增加而逐渐增大.应力随温度变化曲线的分析表明,Ni1-xPtxSi合金硅化物薄膜的应力驰豫温度随Pt含量的增加,从440℃(纯NiSi薄膜)升高到620℃(纯PtSi薄膜).应力驰豫温度的变化影响了最终室温时的应力值.     

Study of Ni/Si(1 0 0) solid-state reaction with Y addition

The characteristics of Ni/Si(1 0 0) solid-state reaction with yttrium (Y) addition are studied in this paper. Film stacks of Ti(20 nm)/TiN(40 nm)/Ni(8 nm)/Y(4 nm)/Ni(8 nm)/Si(1 0 0) and Ti(20 nm)/TiN(40 nm)/Ni(7 nm)/Y(6 nm)/Ni(7 nm)/Si(1 0 0) were prepared by physical vapor deposition. After solid-state reaction between metal films and Si was performed by rapid thermal annealing, various material analyses show that NiSi forms even with the addition of Y, and Ni silicidation is accompanied with Y diffusion in Ni film toward its top surface. The electrical characteristic measurements reveal that no significant Schottky barrier height modulation with the addition of Y occurs.     

Effect of deposition rate and thickness on the structural and electrical properties of evaporated Ni/glass and Ni/Si(1 0 0) thin films

We have studied the effect of substrates [glass and Si(1 0 0)], of Ni thickness (t_Ni) and of the deposition rate [v₁=13 nm/min and v₂=22 nm/min] on the structural and electrical properties of evaporated Ni thin films. The Ni thickness, measured by the Rutherford backscattering (RBS) technique, ranges from 28 to 200 nm. From X-ray diffraction, it was found that all samples are polycrystalline and grow with the 〈1 1 1〉 texture. From the measure of the lattice constant, we inferred that Ni/Si samples are under a higher tensile stress than the Ni/glass ones. Moreover, in Ni/glass deposited at v₁, stress is relived as t_Ni increases while those deposited at v₂ are almost stress-free. The grain size (D) in Ni/glass with low deposition rate monotonously increases (from 54 to 140 Å) as t_Ni increases and are lower than those corresponding to Ni/Si. On the other hand, samples grown at v₂ have a constant D, for small t_Ni with D in Ni/glass larger than D in Ni/Si. Ni/glass deposited at low v₁ are characterized by a higher electrical resistivity (ρ) than those deposited at v₂. For the latter series, ρ is practically constant with t_Ni but decreases with increasing grain size, indicating that diffusion at the grain boundaries rather than surface effect is responsible for the variation of ρ in this thickness range. For the Ni/glass deposed at v₁ and the Ni/Si series, ρ has a more complex variation with thickness and deposition rate. These results will be discussed and correlated.     

Growth and morphology of ultra-thin Ni films on Pd(1 0 0)

A series of Ni films with thickness from 0.2 monolayers (ML) to 12.5 ML were epitaxially grown on a Pd(1 0 0) substrate at room temperature. Growth and morphology were investigated by scanning tunneling microscopy (STM), reflection-high-energy-electron diffraction (RHEED) and Auger electron spectroscopy (AES). We found that the strain relief mechanism for the tetragonal distorted films is related with the appearance of 1 Å high-filaments.     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Formation speed of atomically flat surface on Si (1 0 0) in ultra-pure argon

The flattening speed of the low temperature atomically flattening technology is evaluated in order to apply atomically flat surface of (1 0 0) orientation on large-diameter silicon wafers to the LSI manufacturing. The atomically flatness of the whole surface of wafers with the diameter of 200 mm can be obtained after annealing at 800 °C or above. The process time required to obtain the atomically flatness for the whole wafer surface can be shortened by increasing the annealing temperature as well as by increasing the gas flow rate. With the off angle of 0.50° or below, it was found that only mono-atomic steps appear on the surfaces and the flattening speed is independent of the off angle. These indicate that the process speed is independent of the migration speed of Si atoms on the surface, but depends on the gas replacement efficiency near the Si surface in this technique.     

Electron tunneling in MIS capacitors with the MBE-grown fluoride layers on Si(1 1 1) and Ge(1 1 1): Role of transverse momentum conservation

The current-voltage characteristics of the metal-insulator-semiconductor tunneling structures with calcium fluoride are simulated using different theoretical models. The results are compared to the data of current measurements on the fabricated capacitors with 1-3 nm epitaxial fluorides. Best agreement is achieved imposing a condition of transverse momentum k_⊥ conservation for a tunneling electron. This fact may be treated as an experimental proof for the k_⊥ conservation in the examined high-quality structures which was not directly confirmed on more traditional structures with oxide dielectrics.     

Photomodulated transmittance of GaBiAs layers grown on (0 0 1) and (3 1 1)B GaAs substrates

In this work, photomodulated transmittance (PT) has been applied to investigate the energy gap of GaBiAs layers grown on (0 0 1) and (3 1 1)B GaAs substrates. In PT spectra, a clear resonance has been observed below the GaAs edge. This resonance has been attributed to the energy gap-related absorption in GaBiAs. The energy and broadening of PT resonances have been determined using a standard approach in electromodulation spectroscopy. It has been found that the crystallographic orientation of GaAs substrate influences on the incorporation of Bi atoms into GaAs and quality of GaBiAs layers. The Bi-related energy gap reduction has been determined to be ∼90 meV per percent of Bi. In addition to PT spectra, common transmittance spectra have been measured and the energy gap of GaBiAs has been determined from the square of the absorption coefficient α² around the band-gap edge. It has been found that the tail of density of states is significant for GaBiAs and influences the accuracy of energy gap determination from the α² plot. In the case of PT spectra, the energy gap is determined unambiguously since this technique is directly sensitive to singularities in the density of states.     

Growth and structural properties of crystalline LaAlO3 on Si (0 0 1)

Crystalline LaAlO₃ was grown by oxide molecular beam epitaxy (MBE) on Si (0 0 1) surfaces utilizing a 2 ML SrTiO₃ buffer layer. This SrTiO₃ buffer layer, also grown by oxide MBE, formed an abrupt interface with the silicon. No SiO₂ layer was detectable at the oxide-silicon interface when studied by cross-sectional transmission electron microscopy. The crystalline quality of the LaAlO₃ was assessed during and after growth by reflection high energy electron diffraction, indicating epitaxial growth with the LaAlO₃ unit cell rotated 45° relative to the silicon unit cell. X-ray diffraction indicates a (0 0 1) oriented single-crystalline LaAlO₃ film with a rocking curve of 0.15° and no secondary phases. The use of SrTiO₃ buffer layers on silicon allows perovskite oxides which otherwise would be incompatible with silicon to be integrated onto a silicon platform.     

Praseodymium oxide growth on Si(1 0 0) by pulsed-laser deposition

We report on the pulsed-laser deposition of high-K praseodymium oxide films onto Si(1 0 0) surfaces by laser-ablating a sintered Pr₆O₁₁ target. Optical microscope, SEM, and AFM investigations reveal two kinds of Pr_xO_y-surface structures, which are identified as: (a) large-scaled particles, and (b) ordered structures (rods) of different size with different orientations. The size of the particles increases with laser wavelength. The size of the ordered surface structures strongly depends on the substrate temperature. For the first time, we show characteristic Pr-Raman signals which confirm the crystalline quality of the grown layer. They also indicate that the silicon layer at the Si–Pr_xO_y interface is under compressive stress.     

Growth and fabrication of AlGaN/GaN HEMT based on Si(1 1 1) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm×5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 μm and a gate width of 60 μm demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 μA/mm at the gate voltage of −10 V.     

Growth mechanism of iron nanoparticles on (0 0 0 1) sapphire wafers

Laser ablation of a high purity (99.7%) iron target was used to accomplish the depositions of iron nanoparticles on the (0 0 0 1) face of single crystal sapphire wafers. The nanoparticles were characterized in situ by means of X-ray photoelectron spectroscopy (XPS). The growth mechanism was determined by applying the QUASES-Tougaard methodology to the extended part of the background intensity of the Fe KMM peak in XPS spectra. The heights of nanoparticles obtained are between 3.5 and 6.5 nm. In the first 150 laser pulses, the height of the nanoparticles remained constant while the coverage was increased.     

Crystalline orientation dependence of electrical properties of Mn Germanide/Ge(1 1 1) and (0 0 1) Schottky contacts

We have investigated the crystalline orientation dependence of the electrical properties of Mn germanide/Ge(1 1 1) and (0 0 1) Schottky contacts. We prepared epitaxial and polycrystalline Mn₅Ge₃ layers on Ge(1 1 1) and (0 0 1) substrates, respectively. The Schottky barrier height (SBH) estimated from the current density-voltage characteristics for epitaxial Mn₅Ge₃/Ge(1 1 1) is as low as 0.30 eV, while the SBH of polycrystalline Mn₅Ge₃/Ge(0 0 1) is higher than 0.56 eV. On the other hand, the SBH estimated from capacitance-voltage characteristics are higher than 0.6 eV for both samples. The difference of these SBHs can be explained by the local carrier conduction through the small area with the low SBH regions in the epitaxial Mn₅Ge₃/Ge(1 1 1) contact. This result suggests the possibility that the lowering SBH takes place due to Fermi level depinning in epitaxial germanide/Ge(1 1 1) contacts.     

Influence of AlN buffer layer thickness on the properties of GaN epilayer on Si(1 1 1) by MOCVD

The effect of thickness of the high-temperature (HT) AlN buffer layer on the properties of GaN grown on Si(1 1 1) has been investigated. Optical microscopy (OM), atomic force microscopy (AFM) and X-ray diffraction (XRD) are employed to characterize these samples grown by metal-organic chemical vapor deposition (MOCVD). The results demonstrate that the morphology and crystalline properties of the GaN epilayer strongly depend on the thickness of HT AlN buffer layer, and the optimized thickness of the HT AlN buffer layer is about 110 nm. Together with the low-temperature (LT) AlN interlayer, high-quality GaN epilayer with low crack density can be obtained.     

Stability of Frenkel pairs in Si(1 0 0) surface in the presence of germanium and oxygen atoms

A first-principles pseudo-potential study of Frenkel pair generation close to the Si(1 0 0) surface in the presence of germanium and oxygen atoms is reported. The energies and structures of the defect structures (i.e. vacancy and relaxed tetrahedral Si interstitial) are calculated using supercell with up to 88 atoms. We present results obtained using the generalized gradient approximation (GGA) for the exchange-correlation energy. We examine the effect of the presence of germanium and oxygen atoms on the stability of Frenkel pairs generated near the Si(1 0 0) surface by comparing a number of individual cases, starting from vacancy interstitial pairs situated at various positions. The general tendency of the created interstitials is to climb towards the surface, but they generally remain in subsurface layers, ready to migrate into the layer. This tendency is enhanced by the presence of the Ge and/or O atoms. We show that the formation energy is lower and Si interstitials can be created with energies as low as 1.5 eV.     

Direct epitaxial growth of InP based heterostructures on SrTiO3/Si(0 0 1) crystalline templates

A study of the structural and optical properties of an InAsP/InP quantum well heterostructure grown on a crystalline SrTiO₃ (STO)/Si(0 0 1) template is presented. The mismatch between InP and STO is fully accommodated by an array of geometric dislocations confined at the heterointerface. As a consequence, InP takes its bulk lattice parameter as soon as growth begins, and does not contain threading dislocations related to plastic relaxation. It contains twins related to the initially three-dimensional growth. Despite these twins, photoluminescence from the quantum well is detected at room temperature, showing that STO/Si(0 0 1) templates have an interesting potential for the monolithic integration of III-V semiconductors on silicon.