三维封装中引线键合技术的实现与可靠性

结合半导体封装的发展,研究了低线弧、叠层键合、引线上芯片、外悬芯片、长距离键合和双面键合6种引线互连封装技术;分析了各种引线键合的技术特点和可靠性.传统的引线键合技术通过不断地改进,成为三维高密度封装中的通用互连技术,新技术的出现随之会产生一些新的可靠性问题;同时,对相应的失效分析技术也提出了更高的要求.多种互连引线键合技术的综合应用,满足了半导体封装的发展需求;可靠性是技术应用后的首要技术问题.     

夹层式叠层芯片引线键合技术及其可靠性

随着电子封装技术的快速发展,叠层封装成为一种广泛应用的三维封装技术,该技术能够满足电子产品高性能、轻重量、低功耗、小尺寸等日益增长的需求。针对陶瓷封装腔体中的夹层式叠层芯片结构,键合点与键合引线处于陶瓷外壳空腔中,未有塑封料填充固定,区别于塑封叠层芯片封装器件,优化其引线键合技术,并做了相应可靠性评估试验。键合引线偏移长度最大为0.119 mm,未出现键合引线间隙小于设计值、碰丝短路等情况,为高可靠叠层芯片封装研究提供了参考。     

金属外壳引线键合可靠性研究

引线键合以工艺简单、成本低廉、适合多种封装形式的优势,在连接方式中占主导地位。其中把内部电路与金属外壳内引线柱之间的连接称为引线键合,目前90%以上的封装管脚采用引线键合连接。引线键合强度和可靠性不仅与键合工艺有关（比如键合工艺参数、键合设备、操作技能等因素）,而且与外壳引线的镀覆结构、镀层厚度、内引线柱高度等因素密切相关。文章简要介绍了引线键合工艺的基本原理,通过试验分析并比较了金属外壳镀覆结构、镀层厚度、内引线柱高度对键合可靠性的影响,提出了优化键合可靠性的外壳设计原则。     

MOSFET器件引线键合技术

MOSFET器件由于高阻抗、低功耗等特点,在电脑电源、家用电器和自动控制系统等方面得到广泛应用。但由于其芯片结构的特殊性,在封装制造过程中容易受到静电、应力、环境条件等多种因素的影响。引线键合过程是影响封装成品率的关键工艺环节。引线键合是电子工程互连的重要方式,MOSFET器件通常采用超声键合的工艺进行引线互连。影响引线键合质量的因素较多,其中引线键合工艺、引线材料和设备维护是最重要的三个因素。通过实际生产过程的试验、分析和提炼,研究引线键合技术,总结了引线键合工艺、引线材料和设备维护三个方面的实践经验,为提升和稳定封装成品率提供参考。     

化学镍金基板焊点的失效分析

硅麦克风在消费类电子产品中成功应用,近年来得到了迅猛发展。硅麦克风的封装工艺由于MEMS的特殊结构和封装材料的特殊性,与常见IC封装有许多不同点。其中引线键合工序由于所使用的PCB基板材料特殊的加工工艺,使得引线在PCB基板上的焊点失效成为研究硅麦克风封装成品率和可靠性的一个重要课题。文章重点探讨了硅麦克风封装过程中引线键合工序焊点失效问题,通过不同金线键合方式和金线键合参数的分析,确立了适合于硅麦克风封装的金线键合工艺。     

半导体器件的芯片焊接及内引线键合(二)

三、引线键合微电子器件中内引线键合是把器件芯片金属化电极与器件外壳引出的电极线联结起来。芯片的金属化电极分单层、双层和多层结构,表面层的金属一般是金或铝。目前常用的内引线也是金或铝丝,所以,内引线的键合仍然是金—金系统、金—铝系统和铝—铝系统,内引线键合的方法很多,目前应用较广泛的是热压焊接、超声波键合和热超声焊接的方法。 1、热压焊接热压焊接于1957年在贝尔实验室首先发展起来,至今仍为微电子器件焊接内引线所     

引线键合技术进展

引线键合以工艺简单、成本低廉、适合多种封装形式而在连接方式中占主导地位.对引线键合工艺、材料、设备和超声引线键合机理的研究进展进行了论述与分析,列出了主要的键合工艺参数和优化方法,球键合和楔键合是引线键合的两种基本形式,热压超声波键合工艺因其加热温度低、键合强度高、有利于器件可靠性等优势而取代热压键合和超声波键合成为键合法的主流,提出了该技术的发展趋势,劈刀设计、键合材料和键合设备的有效集成是获得引线键合完整解决方案的关键.     

多排焊盘外壳封装IC金丝球焊键合技术

在多层多排焊盘外壳封装电路的引线键合中,由于键合的引线密度较大,键合引线间的距离较小,键合点间的距离也较小,在电路的键合中就需要对键合点的位置、质量、键合引线的弧线进行很好的控制,否则电路键合就不能满足实际使用的要求。文中就高密度多层、多排焊盘陶瓷外壳封装集成电路金丝球焊键合引线的弧线控制、外壳焊盘常规植球键合点质量问题进行了讨论,通过对键合引线弧线形式的优化以及采用"自模式"植球键合技术大大提高了电路键合的质量,键合的引线达到工艺控制和实际使用的要求。同时,外壳焊盘上键合的密度也得到了提高。     

把握市场机遇的绝缘键合引线技术

去年，Microbonds公司面向大众推出了他们的绝缘键合引线，并由此宣布加入复合引线键合机和设备制造商的行列。他们进一步采取措施，通过获得Tanaka Denshi Kogyo公司的认可，使这项技术立足于市场，该公司是裸金丝键合引线的全球供应商。     

引线键合技术的现状和发展趋势

作为目前和可预见的将来半导体封装内部连接的主流方式,引线键合技术不断变化以适应各种半导体封装新工艺和材料的要求和挑战。以引线键合设备为中心,全面深入地综述了引线键合技术在引线间距(键合精度)、生产效率(键合速度)、键合质量与可靠性(超声焊接、熔球过程及线弧形状的精确控制)等方面的当前状况。同时也总结了铜互联材料、低介电常数材料、有机(柔性)基底材料、多芯片模块(MCM)和层叠芯片(stackeddie)等半导体封装新趋向对引线键合技术的影响。在此基础上对引线键合技术在未来中长期的发展趋势进行了展望。     

IC封装中键合线传输结构的仿真分析

随着高频高速集成电路制造工艺的不断进步,电子封装技术的发展也登上了一个新高度。作为微电子器件制造过程中的重要步骤之一,封装中的传输线、过孔、键合线等互连结构都可能对电路的性能产生影响,因此先进的集成电路封装设计必须要进行信号完整性分析。介绍了一种键合线互连传输结构,采用全波分析软件对模型进行仿真,着重分析与总结了键合线材料、跨距、拱高以及微带线长度、宽度五种关键设计参数对封装系统中信号完整性的影响,仿真结果对封装设计具有实际的指导作用。     

Overview of wire bonding using copper wire or insulated wire

Wire bonding using copper or insulated wire leads to many advantages and new challenges. Research is intensively performed worldwide, leading to many new findings and solutions. This article reviews recent advances in wire bonding using copper wire or insulated wire for advanced microelectronics packaging. Journal articles, conference articles and patents published or issued recently are reviewed. The benefits and problems/challenges related to wire bonding using copper wire or insulated wire such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, and stiff wire on weak support structures, are briefly analyzed. A number of solutions to the problems and recent findings/developments related to wire bonding using copper wire or insulated wire are discussed. With the references provided, readers may explore more deeply by reading the original articles and patent documents.     

一种基于低温共烧陶的无引线键合封装

为提高微机电系统(MEMS)加速度计的可靠性,减小因为引线键合断裂造成的传感器失效,该文设计了一种基于低温共烧陶瓷的无引线键合封装。该封装采用阳极键合技术将低温共烧陶瓷基板与芯片连接,同时将电路转接板同步集成。结果表明,该封装结构可减小传感器的封装尺寸,有效提高了MEMS加速度计的可靠性。     

共漏极双功率MOSFET封装研究

针对适用于锂电池保护电路特点要求的共漏极功率MOSFET的封装结构进行了研发和展望.从传统的TSSOP-8发展到替代改进型SOT-26,一直到芯片级尺寸的微型封装外形,其封装效率越来越高,接近100%.同时,在微互连和封装结构的改进方面,逐渐向短引线或焊球无引线、平坦式引脚、超薄型封装和漏极焊盘散热片暴露的方向发展,增...     

Insulated Cu wire free air ball characterization

Insulated Cu wire technology has immense potential for fine pitch wire bonding interconnection. Understanding the behavior of the insulated Cu free air ball (FAB) formation is crucial for wire bonding process. The FAB formation, size, shape and cleanliness under different conditions for 20 μm insulated Cu wire were investigated using SEM, FESEM and FTIR surface analysis. The results were compared with that of bare Cu wire. Consistently spherical residue free FAB of insulated Cu wire were formed using forming gas. The samples with insulated Cu wire consistently produced larger FAB than that of bare Cu wire, indicating that the energy required for free air ball formation is lower. Basic bonding performances in terms of ball bond strength, intermetallic (IMC) coverage growth and stitch bond strength of insulated Cu wire at time zero are also discussed in the paper.     

多层陶瓷外壳的失效分析和可靠性设计

文章对多层陶瓷外壳的失效模式,包括陶瓷底座断裂失效、绝缘电阻失效、断路和短路失效、外引线和无引线外壳引出端焊盘与外电路连接失效、电镀层锈蚀失效、密封失效、键合和芯片剪切失效和使用不当造成失效等进行讨论,并对这些失效的失效机理进行了分析,根据以上的失效模式及其失效机理分析,对多层陶瓷外壳的可靠性设计进行了探讨。     

Optimal design for a ball grid array wire bonding process using aneuro-genetic approach

This study presents an integrated method in which neural networks, genetic algorithms, and exponential desirability functions are used to optimize the ball grid array (BGA) wire bonding process. As widely anticipated, the BGA package will become the fastest-growing semiconductor package and push integrated circuit (IC) packaging to higher level of compactness and density. However, wire bonding in BGA is difficult owing to its high input/output (I/O) count, fine pitch wire bonds, and long wire lengths. This study addresses two fundamental issues in the semiconductor assembly facility on its quest toward a defect-free manufacturing environment. First, the problem of exploring the nonlinear multivariate relationship between parameters and responses and second, obtaining the optimum operation parameters with respect to each response in which the process should operate. The implementation for the proposed method was carried out in an IC assembly factory in Taiwan; results in this study demonstrate the practicability of the proposed approach     

Two capillary solutions for ultra-fine-pitch wire bonding and insulated wire bonding

In this article, the new challenges and requirements in wire bonding are discussed, the problems in ultra-fine-pitch wire bonding and insulated wire bonding are analyzed, and then two capillary solutions to the problems are presented. Actual bonding experiments using the new capillaries were carried out and the results were satisfactory. Compared to the standard design, a new capillary design has a larger inner chamfer, a larger chamfer diameter and a smaller chamfer angle. This new capillary design has proved to improve the ball bondability and smaller ball size control for ultra-fine pitch wire bonding. A unique surface characteristic on the capillary tip surface has also been derived. The new finishing process developed creates a new surface morphology, which has relatively deep lines with no fixed directions. Compared to the standard capillary, this capillary has less slipping between the wire and the capillary tip surface in contact, and provides better coupling effect between them and better ultrasonic energy transfer. This capillary has been used to effectively improve the bondability of the stitch bonds for insulated wire bonding.     

A 1.9-GHz CMOS VCO with micromachined electromechanically tunablecapacitors

This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-μm CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively