Statistical simulation methodology for sub- 100nm memory design

A new statistical simulation methodology under process variations in deep sub-micron technology is described. By dividing the overall memory system into sub-blocks and running Monte Carlo simulations locally, significant reduction in the statistical simulation time is achieved. A novel methodology to combine the simulation results and accurately predict the read access failure of the overall system is also presented. This allows allocation of design margins and setting of design guidelines for each sub-block in the early design stage.     

Variability-insensitive scheme for NAND flash memory interfaces

A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability     

NAND flash memory technology utilizing fringing electric field

In this review article, basic properties of NAND flash memory cell strings which consist of cells with virtual source/drain (S/D) (or without S/D) were discussed. The virtual S/D concept has advantages of better scalability, less cell fluctuation due to effectively longer channel length at the same technology node, and less program disturbance. The fringing electric field from the control-gate and/or the floating-gate is essential to induce the virtual S/D (charges) in the space region of the body between control-gates and becomes effective as cell size shrinks. A cell string consisting of planar channel silicon-oxide-nitride-oxide-silicon (SONOS) cells formed in bulk Si substrate needs to have a bit-line body doping of ～5 × 10¹⁷ cm^?3 in the channel and a less doping in the space region to keep high bit-line read current. The floating gate (FG) flash memory cell string gives larger bit-line current compared to that of SONOS flash memory cell string at given similar body doping. Non-planar channel cells like arch and fin-type body structures were more effective to focus the fringing electric field on the space region. The virtual S/D concept is also useful in 3-dimensional (3-D) stacked NAND flash memory where thin film (or nanowire, nanotube) body is adopted.     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

Effects of floating-gate interference on NAND flash memory celloperation

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V _T shift of a cell proportional to the V_T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-μm design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors     

发展3D NAND闪存的意义

首届IC咖啡国际智慧科技产业峰会于2017年1月14日在上海召开,长江存储集团公司CEO杨士宁介绍了对存储器市场的看法,及选择3D NAND闪存作为主打产品的战略思考.     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses

For the first time, an innovative programming methodology based on the use of ultra-short voltage pulses is applied in NAND flash architecture. The methodology starts from the physics of SILC dynamics and oxide damage, and relies on the trade-off between duration and amplitude of short voltage programming pulses, minimizing the creation of new traps in the tunnel oxide. The short pulses programming technique is applied on a small 50 nm NAND array designed for multibit application. Benefits of the short-pulse operation lie in that data retention and endurance which show meaningful improvements. The result is relevant for application in multibit technology, and opens the way to more aggressive cell scaling rules.     

Short-channel effects in sub-100 nm GaAs MESFETs

GaAs MESFETs with gate lengths ranging from 260 nm down to 30 nm have been fabricated using high resolution electron-beam lithography. The DC characteristics including transconductance, output conductance, threshold voltage, and subthreshold current of these devices have been measured. Short-channel effects manifested as a negative shift in threshold voltage and an increase in output conductance have been observed as the gate length decreased. These effects become pronounced as the device aspect ratio (gate-length/channel thickness) falls below 5. Subthreshold current increased with a decrease in gate length and is actually an exponential function of the gate bias for gate dimensions below 100 nm. Also, subthreshold current is an increasingly more sensitive function of the drain-to-source voltage as the gate-length is reduced. The observed effects are attributed to the space charge limited electron injection into the GaAs buffer layer under the channel.<>     

一种基于NAND闪存高效的页面替换算法

针对不同NAND闪存读写操作成本比例的不同,提出一种具有高效页面替换功能的EPRA算法。在内存中,每个受害者候选页被分成固定数量的闪存页面。EPRA给每个受害者候选页分配权重值,在选择与修改页面时对权重进行调节,从候选页中选择具有最小权重值的页面作为受害者页。EPRA算法把受害者页中分为热的闪存页和冷的闪存页,并把这些数据写到NAND闪存中不同空闲的块中。仿真实验结果表明,EPRA算法使用在不同种类的NAND闪存中时,性能优于现有的页面替换算法。     

Data retention characteristics of MANOS-type flash memory device with different metal gates at various levels of charge injection

We investigated the impact of charge injection and metal gates (Al and Pt) on the data retention characteristics of metal–alumina–nitride–oxide–silicon (MANOS) devices for NAND flash memory application. Through the theoretical and experimental results, the highly injected charge (ΔV_TH) could cause the band bending of Al₂O₃, which reduced the tunneling distance across Al₂O₃. Thus, the dominant charge loss path is not only toward SiO₂ but also toward Al₂O₃ direction. Compared to low-metal work function (Ф_M), ONA stack with high-Ф_M showed better data retention characteristics, even if ΔV_TH is high. This could be explained by Fermi level alignment for different Ф_M, which results in the reduction of electric field across the Al₂O₃ compensated by the ΔФ_M (Ф_Pt ? Ф_Al).     

Nano-power subthreshold current-mode logic in sub-100 nm technologies

The feasibility of robust MOS current-mode logic (MCML) digital circuits operated in subthreshold regime is investigated. The design of a subthreshold MCML inverter gate in a 90 nm CMOS technology is presented together with the evaluation of its DC performance.     

Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory

Owing to its desirable characteristics, flash memory has become attractive to different hardware vendors as a primary choice for data storage. However, because of a limited number of block-erase lifecycles, it has become mandatory to redesign the existing approaches to maximize the flash memory lifetime. Wear-leveling is a mechanism that helps to evenly distribute erase operations to all blocks and enhance lifetime. This research proposes probability-based static wear-leveling. Based on the Markov Chain theory, the future state depends on the present state. Mapping is implemented according to the present visit probability of each logical block in the next state. In each state, the wear-leveling distribution is computed using the standard deviation to determine whether it exceeds the threshold. If it does exceed the threshold, wear-leveling is maintained throughout all blocks in the flash memory by swapping the hot blocks with cold blocks. Using real system-based traces, we have proved that our proposal outperforms the existing design in terms of wear-leveling.     

A 144-Mb, eight-level NAND flash memory with optimized pulsewidthprogramming

We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-μm CMOS process, resulting in a 104.2-mm² die size and a 1.05-μm² effective cell size     

Thermal conduction in sub-100 nm transistors

Heat conduction in integrated circuits spans length scales across several orders of magnitude: From the lattice spacing at a few Angstroms to the substrate thickness at hundreds of micrometers. The smaller length scale becomes increasingly important in devices with feature size well below 100 nm. This paper provides an overview of sub-continuum electro-thermal transport. We use the phonon Boltzmann transport equation to model heat conduction in the device and show that phonons emitted by hot electrons in the drain create a phonon hotspot. The resulting non-equilibrium leads to increased thermal resistance within the device. At the limits of scaling, the resistance is comparable to that due to the substrate and packaging.     

Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory

The investigations on the nanowire width (W) dependence of memory performance including P/E (programming and erasing) speed, data retention time and endurance characteristics in nanowire SONOS flash memory have been performed through the measurement and the device simulation. From measured results, a narrow device has advantages in terms of a fast P/E speed and the endurance characteristics. However, a narrow device has disadvantage in terms of the decreased data retention time. Another disadvantage of a narrow device is expected to the large power consumption due to large GIDL (Gate Induced Drain Leakage) current. The device simulation was performed to explore the causes for a fast P/E speed, an enhanced endurance characteristics and the reduced data retention time in narrow devices.     

Inverse modeling of sub-100 nm MOSFETs using I-V and C-V

Direct quantitative two-dimensional (2D) profile characterization of state-of-the-art MOSFETs continues to be elusive. In this paper, we present a comprehensive indirect methodology that achieves that for sub-100 nm MOSFETs using combined current-voltage (I-V) and capacitance-voltage (C-V) data. An optimization loop minimizes the error between simulated and measured electrical characteristics by adjusting parameterized doping profiles. This technique possesses high sensitivity to critical 2D doping in the source/drain extensions and channel region as well as to structural details such as t_ox and physical gate length. Here we demonstrate the technique by characterizing two NMOS families (t_ox=3.3 nm and 1.5 nm with effective channel lengths down to 50 nm). We then follow up with an evaluation of the ability of inverse modeling to capture modern profiles using simulated devices and I-V data. We show that extracted profiles exhibit decreased root mean square error (RMSE) as the doping parameterization becomes increasingly comprehensive of doping features (i.e., implants or doping pile-up)     

Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories

In this paper we propose to study different ways to extract the values of parasitic capacitances in 90 nm and 22 nm NAND Flash memories. Indeed, these parasitic capacitances between cells in the array can modify applied polarizations and can disturb the functioning of the whole array. Their impact increases when the cell size is reduced, especially as the ultimate size of the 22 nm node is reached. We develop 3D TCAD simulations to extract parasitic capacitances as well as measurements on specific test structures or geometrical calculations, showing their increasing importance in the future technologies, especially for 22 nm node.     

Technology innovation and process integrations for sub-100nm gate patterning

This paper presents a brief overview of the Applied Centura(R)DPS(R)system,configured with silicon etch DPS Ⅱ chamber, with emphasis on discussing tuning capability for CD uniformity control. It also presents the studies of etch process chemistry and film integration impact for an overall successful gate patterning development. Discussions will focus on resolutions to key issues, such as CD uniformity, line-edge roughness, and multilayer film etching integration.     

A 3.3 V 32 Mb NAND flash memory with incremental step pulseprogramming scheme

While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm² die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA