源科磐龙系列XMC固态存储卡为数据安全保驾护航

源科推出的磐龙系列第一代XMC固态存储卡（RCVI—MU3XXXXX系列SolidStateStorageCard）,按照VITA42标准设计,采用风冷散热的单卡形式,支持SLC和MI,C两种类型的Flash存储介质,容量范围分别达到32～128GB（SLC）和32～512GB（MLC）。与机械盘相比,RCV—I—MU3XX—XXX系列XMC固态存储卡不采用任何机械活动部件,具有性能优越、可靠性高、容量大、全固态、抗震、宽温以及功耗低等优点,能够适应各种灵活的应用环境。     

Emulex支持HP ProLiant Gen9平台优化

近日,网络连接、监控和管理领域的领导者Emulex公司宣布了一系列用于全新HP ProLiant Gen9机架和刀片服务器的I/O连接解决方案,进而为虚拟桌面基础架构（VDI）、大数据分析等下一代工作负载,以及新兴计算架构（包括面向电信和OpenStack或基于OpenCompute的云计算的NFV网络功能虚拟化）提供支持。利用Emulex的高性能I/O连接,客户可以扩展工作负载,优化关键应用的应用性能,并缩短迁移虚拟工作负载的时间,进而提高虚拟化灵活性。     

基于非均匀感知策略的MLC闪存系统

面向多级单元（Multi-Level Cell,MLC）的LDPC码的最小和（Min-Sum,MS）译码算法译码性能取决于码字中每个比特对应的对数似然比（Log-Likelihood Ratio,LLR）的准确度,然而基于均匀感知策略的MLC电压读取方法需要提高感知精度才能获取精度高的LLR值,这将增加MLC闪存单元的读取时间. 针对这种情况,本文提出一种基于非均匀感知策略的MLC闪存MS译码算法,该算法对MLC闪存阈值电压的感知采用非均匀的感知策略. 在相同的感知精度下,相比于均匀感知策略,非均匀感知策略能够提高LLR的准确度,获得更低的原始比特错误率. 仿真结果表明,在MLC闪存信道条件下,该算法既可保证MLC闪存单元可靠性,而且保持较快的读取速度,从而实现了译码速度和译码性能间的良好折衷.     

一种基于请求大小的固态盘I／O调度算法

对于同类型的I／O请求,基于闪存固态盘的请求响应时间与请求大小基本呈线性比例关系,并且固态盘的读写性能具有非对称性。针对该特性,提出一种基于请求大小的固态盘I／O调度（SIOS）算法,从I／O请求平均响应时间的角度提高固态盘设备的I／O性能。根据读写性能的非对称性,对读写请求进行分组并且优先处理读请求。在此基础上首先处理等待队列中的小请求,从而减少队列中请求的平均等待时间。采用SLC和MLC2种类型的固态盘进行实验,在5种测试负载的驱动下与Linux系统中的3种调度算法进行比较,对于SLC固态盘,SIOS平均响应时间分别减少18．4％、25．8％、14．9％、14．5％和13．1％,而对于MLC固态盘,平均响应时间分别减少16．9％、24．4％、13．1％、13．0％和13．7％,结果表明,SIOS能有效减少I／O请求的平均响应时间,提高固态盘存储系统的I／O性能。     

面向托管的数据库即服务系统及资源优化技术

数据库即服务（DBaaS）是云计算的一个研究热点,而数据应用托管则是当前DBaaS的一个重要应用领域。为满足行业数据应用托管中对DBaaS提出的数据隔离、性能隔离及可靠性保障等方面的要求,提出一种无共享架构下基于虚拟机、支持副本的多租户数据托管方法及相应的数据库即服务系统。针对该系统中面向租户的虚拟机资源（CPU、内存等）动态优化这一核心问题,建立了基于虚拟机的系统资源效用函数和数据库性能计算模型,并在基础上给出了一种根据租户数据请求负载并采用贪心方式的虚拟机资源动态优化算法。结合科技信息服务数据库托管应用示例进行了实验,实验结果表明提出的方法可以根据各个租户的数据库负载动态优化虚拟机的资源分配,能够在满足性能需求同时达到了提高系统资源利用率的目的。     

基于Nginx的DRC集群动态负载均衡策略

面向数据的体系架构（DOA）为海量异构数据流通共享提供了新的有效解决方案。而数据注册中心（DRC）作为DOA的核心部件,它的访问性能尤为关键。针对高并发访问带来的DRC集群服务过载问题,采用Nginx反向代理负载均衡技术处理高并发访问。对Nginx的负载策略进行分析优化,提出一种由动态配置、负载收集、算法调度组成的动态负载均衡策略,并在负载调度模块对Nginx加权最小连接调度算法（WLC）进行改进,通过自适应权值不断调度下一个周期内性能最优的节点来处理请求。通过高并发性能测试验证了所提出的负载均衡策略在DRC集群中能更有效处理大流量的访问需求,提高集群的资源利用率和缩短请求响应时间。     

一种适用于MLC闪存的CCI噪声均衡化算法

随着多级单元(Multi-Level Cell,MLC)闪存存储密度的增加,单元间干扰(Cell-to-Cell Interference,CCI)成为影响NAND闪存可靠性的主要噪声。在深入研究MLC闪存模型和CCI噪声模型的基础上,提出了一种MLC闪存的CCI噪声均衡化算法。该算法通过估计CCI干扰强度进而对感知MLC阈值电压进行补偿,可以更准确地读取MLC单元中存储的信息。仿真结果表明,在MLC闪存信道条件下,CCI噪声均衡化算法可以有效减少相邻状态的阈值电压交叉现象,有助于降低原始比特错误率,增强MLC闪存的可靠性。     

基于软件定义网络的分层式控制器负载均衡机制

针对软件定义网络（SDN）多控制器负载均衡过程中控制器之间通信开销大以及控制器吞吐量低等问题,提出一种分层式控制器负载均衡机制。基于分层式架构,通过超级控制器与域控制器协作完成负载均衡,并采用预定义负载阈值以减少域控制器与超级控制器之间的消息交换开销;同时,该机制可以有效选择出过载最重的域控制器,并从该过载域控制器所控制的交换机中选取多个符合迁移标准的交换机,将其同时分别迁移到多个综合性能高的域控制器上,从而解决多控制器间负载不均衡问题。实验结果表明,与层次式SDN控制器协同负载均衡方案（COLBAS）以及用于控制器负载均衡的动态和自适应算法（DALB）相比,所提机制系统的消息数量降低了约79个百分点,且该系统的吞吐量分别比DALB、COLBAS分别提高了约8.57%、52.01%。所提机制能够有效降低通信开销,并提高系统吞吐量,有更好的负载均衡效果。     

基于AWGR的光电混合数据中心网络架构设计

随着云计算需求与服务器数量的不断增长,数据中心网络（data center network,DCN）面临可扩展性、低成本、低能耗、高带宽等一系列挑战。提出了一种基于阵列波导光栅路由器（arrayed waveguide grating router,AWGR）的光电混合数据中心网络架构。该混合架构由AWGR提供大容量光波长路由,由电分组交换机提供突发分组交换,同时满足大象流量和老鼠流量的需求。AWGR是无源光器件,将有效降低网络能耗,提高网络可靠性,与光电路交换机相比,可降低配置时间延迟。分析了在架顶交换机上分别采用全固定波长激光器（方案1）、混合固定波长激光器和波长可调谐激光器（方案2）、全波长可调谐激光器作为光源（方案3）的3种架构方案。对3种架构方案的成本和能耗进行了数值分析和计算,同时对网络性能进行了理论分析与仿真。成本和能耗数值分析结果显示：3种架构方案的成本与能耗随着服务器数量的增加不断增长,方案3增长的速度最快,方案1增长的速度最慢,方案2介于两者之间。网络性能仿真结果显示：在不同网络负载情况下,方案2架构的网络吞吐量和波长请求阻塞率与方案3接近,远高于方案1,因此混合固定波长激光器与波长可调谐激光器的方案2具备较好的性价比。     

嵌入式系统中MLC闪存驱动研究

MLC闪存高密度、低成本的特点,适于做海量存储器.文中以在WinCE6.0平台下实现高性能的MLC闪存驱动为目的,介绍了ARM嵌入式系统中NAND FLASH控制器的工作原理;讨论了WinCE下闪存驱动可采用的两种架构,并在新的MDD、PDD闪存驱动架构下实现了该驱动;介绍并实现了双片操作命令操作;介绍了DMA的工作原理,并实现了DMA编程.测试表明,较之前传统架构及传统操作命令,写入速度提高1.8倍.读出速度提高1.3倍,可靠性也大幅提高.该设计方案可放应用于需要大容量存储的嵌入式系统中.     

ComboFTL: Improving performance and lifespan of MLC flash memory using SLC flash buffer

Multi-level cell (MLC) flash memory has lower bit cost compared to single-level cell (SLC) flash memory. However, there are several obstacles to the wide use of MLC flash memory, including slow write performance and shorter lifespan. To improve the performance and lifespan of MLC flash memory, we propose an FTL (flash translation layer) for MLC flash memory, called ComboFTL. By exploiting the SLC mode of MLC flash memory, ComboFTL manages a small SLC region for hot data and a large MLC region for cold data. To provide the performance and lifespan similar to those of SLC flash memory, ComboFTL identifies the hotness/coldness of data effectively. It can also adjust its several policies based on workload changes. Our experimental results showed that ComboFTL improves the write performance and lifespan of MLC flash memory significantly.     

一种闪存敏感的多级缓存管理方法

基于闪存的固态硬盘(solid state driver,简称SSD)已经广泛应用于各种移动设备、PC机和服务器.与磁盘相比,尽管SSD具有数据存取速度高、抗震、低功耗等优良特性,但SSD自身也存在读写不对称、价格昂贵等不利因素,这使得SSD 短期内不会完全取代磁盘.将SSD和磁盘组合构建混合系统,可以发挥不同的硬件特性,提升系统性能.基于 MLC 型 SSD 和 SLC 型 SSD 之间的特性差异,提出了一种闪存敏感的多级缓存管理策略——FAMC.FAMC将SSD用在内存和磁盘之间作扩展缓存,针对数据库系统、文件管理中数据访问的特点,有选择地将内存牺牲页缓存到不同类型的SSD.FAMC同时考虑写请求模式和负载类型对系统性能的影响,设计实现对SSD友好的数据管理策略.此外,FAMC基于不同的数据置换代价提出了适用于SSD的缓冲区管理算法.基于多级缓存存储系统对FAMC的性能进行了评测,实验结果表明,FAMC可以大幅度降低系统响应时间,减少磁盘I/O.     

A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk

This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.     

Design and implementation of MLC NAND flash-based DBMS for mobile devices

Recently, Multi-Level Cell (MLC) NAND flash memory is becoming widely used as storage media for mobile devices such as mobile phones, MP3 players, PDAs and digital cameras. MLC NAND flash memory, however, has some restrictions that hard disk or Single-Level Cell (SLC) NAND flash memory do not have. Since most traditional database techniques assume hard disk, they may not provide the best attainable performance on MLC NAND flash memory. In this paper, we design and implement an MLC NAND flash-based DBMS for mobile devices, called AceDB Flashlight, which fully exploits the unique characteristics of MLC NAND flash memory. Our performance evaluations on an MLC NAND flash-based device show that the proposed DBMS significantly outperforms the existing ones.     

基于多级磁自旋存储器的Cache调度策略的设计

多级磁自旋存储器(Multi-Level Cell Spin-Transfer Torque RAM,MLC STT-RAM)可在一个存储单元中存储多个比特位,有望取代SRAM用于构建大容量低功耗的最后一级Cache(Last Level Cache,LLC)。MLC STT-RAM的静态功耗在理论上为0,且拥有高密度和优秀的读操作特性,但它的缺陷在于低效的写操作。针对这一问题,在MLC STT-RAM Cache hard/soft逻辑分区结构 的基础上,实现了MLC STT-RAM LLC写操作密集度预测技术以及相应Cache结构的设计。通过动态预测写操作密集度较高的Cache块,帮助MLC STT-RAM LLC减少执行写操作的代价。预测的基本思想是利用访存指令地址与相应Cache块行为特征的联系,根据预测结果决定数据在LLC中的放置位置。实验结果显示,在MLC STT-RAM LLC中应用写操作密集度预测技术,使得写操作动态功耗降低6.3%的同时,系统性能有所提升。     

Linked instruction caches for enhancing power efficiency of embedded systems

The power consumed by memory systems accounts for 45% of the total power consumed by an embedded system, and the power consumed during a memory access is 10 times higher than during a cache access. Thus, increasing the cache hit rate can effectively reduce the power consumption of the memory system and improve system performance. In this study, we increased the cache hit rate and reduced the cache-access power consumption by developing a new cache architecture known as a single linked cache (SLC) that stores frequently executed instructions. SLC has the features of low power consumption and low access delay, similar to a direct mapping cache, and a high cache hit rate similar to a two way-set associative cache by adding a new link field. In addition, we developed another design known as a multiple linked caches (MLC) to further reduce the power consumption during each cache access and avoid unnecessary cache accesses when the requested data is absent from the cache. In MLC, the linked cache is split into several small linked caches that store frequently executed instructions to reduce the power consumption during each access. To avoid unnecessary cache accesses when a requested instruction is not in the linked caches, the addresses of the frequently executed blocks are recorded in the branch target buffer (BTB). By consulting the BTB, a processor can access the memory to obtain the requested instruction directly if the instruction is not in the cache. In the simulation results, our method performed better than selective compression, traditional cache, and filter cache in terms of the cache hit rate, power consumption, and execution time.     

A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems

Similar to traditional NAND flash memory, triple-level cell (TLC) flash memory is used as secondary storage to meet the fast growing demands on storage capacity. TLC flash memory exhibits attractive features such as shock resistance, high density, low cost, non-volatility and low access latency natures. However, TLC flash memory also has some extra limitations, such as write disturbance, low performances and very limited cycles compared to single-level cell (SLC) flash memory.In this paper, we propose a workload-aware flash translation layer, named Balloon-FTL, for the TLC/SLC dual-mode flash memory, to improve performance and lifespan of the system. We first build a workload identifier module with genetic algorithm to dynamically allocate TLC/SLC capacity based on different workloads, and produce the suitable data allocation to achieve a balanced write distribution in flash memory with low memory access cost. The basic idea is to classify metadata/userdata according to their access pattern, and allocate low-latency SLC and high-density TLC mode blocks for write-intensive metadata and a large quantities userdata, respectively. We then propose a special hybrid mapping strategy for the TLC/SLC dual-mode flash memory to improve the performance. Experimental results show that Balloon-FTL can effectively improve the performance and lifespan of the TLC/SLC dual-mode flash memory in embedded systems.     

Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures

Scheduling periodic tasks onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an Integer Linear Programming (ILP) based framework that maps a given task set onto an Heterogeneous Multiprocessor System-on-Chip (HMPSoC) architecture. Our framework can be used with several objective functions; minimizing energy consumption, minimizing cost (i.e., the number of heterogeneous processors), and maximizing reliability of the system under performance constraints. We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to maximize reliability. We illustrate the effectiveness of our approach through several experiments, each with a different number of tasks to be scheduled. We also propose two heuristics based on Earliest Deadline First (EDF) algorithm for minimizing energy under performance and cost constraints. Our experiments on generated task sets show that ILP-based method reduces the energy consumption up to 62% percent against a method that does not apply DVS. Heuristic methods obtain promising results when compared to optimal results generated by our ILP-based method.     

Exploiting performance counters to predict and improve energy performance of HPC systems

Hardware monitoring through performance counters is available on almost all modern processors. Although these counters are originally designed for performance tuning, they have also been used for evaluating power consumption. We propose two approaches for modelling and understanding the behaviour of high performance computing (HPC) systems relying on hardware monitoring counters. We evaluate the effectiveness of our system modelling approach considering both optimizing the energy usage of HPC systems and predicting HPC applications’ energy consumption as target objectives. Although hardware monitoring counters are used for modelling the system, other methods–including partial phase recognition and cross platform energy prediction–are used for energy optimization and prediction. Experimental results for energy prediction demonstrate that we can accurately predict the peak energy consumption of an application on a target platform; whereas, results for energy optimization indicate that with no a priori knowledge of workloads sharing the platform we can save up to 24% of the overall HPC system’s energy consumption under benchmarks and real-life workloads.     

Writeback throttling in a virtualized system with SCM

Storage class memory (SCM) has the potential to revolutionize the memory landscape by its non-volatile and byte-addressable properties. However, there is little published work about exploring its usage for modern virtualized cloud infrastructure. We propose SCM-vWrite, a novel architecture designed around SCM, to ease the performance interference of virtualized storage subsystem. Through a case study on a typical virtualized cloud system, we first describe why current writeback manners are not suitable for a virtualized environment, then design and implement SCM-vWrite to improve this problem. We also use typical benchmarks and realistic workloads to evaluate its performance. Compared with the traditional method on a conventional architecture, the experimental result shows that SCM-vWrite can coordinate the writeback flows more effectively among multiple co-located guest operating systems, achieving a better disk I/O performance without any loss of reliability.