Ultrafast photonic ATM switch with optical output buffers

An ultrafast photonic asynchronous transfer mode (ATM) (ULPHA) switch based on a time-division broadcast-and-select network with optical output buffers is presented. The ULPHA switch has an ultra-high throughput and excellent traffic characteristics, since it utilizes ultrashort optical pulses for cell signals and avoids cell contentions by novel optical output buffers. Feasibility studies show that an 80×80 ULPHA switch with 1-Gb/s input/output is possible by applying the present technology, and that more than 1 Tb/s is possible by making a three-stage network using such switches. As an experimental demonstration, 4-bit 40-Gb/s optical cells were generated and certain cells were selected at an output on a self-routing basis. With its high throughput and excellent traffic considerations, the ULPHA switch is a strong candidate for a future large-capacity optical switching node     

用于10^3Mbit网络的光电开关器件

介绍用于１０＾１０Ｍｂｉｔ网络的一种光电异步变换模式形状器件。这种光电异步变换模式开关使用垂直于表面传输的电光器件，通过采用光学缓冲存贮和光学自排程电路的新颖两维光功能器件能够实现很大容量的网络。     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

A prototype broadcast-and-select photonic ATM switch with a WDMoutput buffer

A rack-mounted prototype of a broadcast-and-select (B and S) photonic ATM switch is fabricated. This switch has an optical output buffer utilizing wavelength division multiplexed (WDM) signals. The WDM technology solves. The cell-collision problem in a broadcast-and-select network and leads to a simple network architecture and the broadcast/multicast function. The prototype can handle 10-Gb/s nonreturn-to-zero (NRZ) coded cells and 5-Gb/s Manchester-coded cells and has a switch size of four. In this prototype, the level and timing design are key issues. Cell-by-cell level fluctuation is overcome by minimizing the loss difference between the optical paths and adopting a differential receiver capable of auto-thresholding. The temperature control of delay lines was successful in maintaining the phase synchronization. Using these techniques, we are able to provide a WDM highway with a bit error rate of less than 10^-12. Fundamental photonic ATM switching functions, such as optical buffering and fast wavelength-channel selection, are achieved. We show our experimental results and demonstrate the high performance and stable operation of a photonic ATM switch for use in high-speed optical switching systems as an interconnect switch for a modular ATM switch and an ATM cross-connect switch     

32×32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 μm CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32×32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32×32 switching board to achieve large-scale switching systems such as 256×256 or 1024×1024 switches are discussed     

Large-scale WDM star-based photonic ATM switches

This paper describes the large-scale photonic asynchronous transfer mode (ATM) switching systems being developed in NTT Laboratories. It uses wavelength division multiplexing (WDM) techniques to attack 1 TB/s throughput. The architecture is a simple star with modular structure and effectively combines optical WDM techniques and electrical control circuits. Recent achievements in important key technologies leading to the realization of large-scale photonic ATM switches based on the architecture are described. We show that we can obtain a 320 Gb/s system that can tolerate the polarization and wavelength dependencies of optical devices. Our experiments using rack-mounted prototypes demonstrate the feasibility of our architecture. The experiments showed stable system operation and high-speed WDM switching capability up to the total optical bandwidth of 12.8 nm, as well as successful 10 Gb/s 4×4 broadcast-and-select and 2.5 Gb/s 16×16 wavelength-routing switch operations     

Optical input buffers for the HiPower photonic ATM switch-analysisand experiments

We describe an optical input buffer for the HiPower photonic ATM switch. This buffer can control the cell throughput in accordance with back pressure signals and incoming optical cells. We analyze the cell loss probability of the optical input buffer. Only a small buffer size of five is needed to obtain a cell loss probability of less than 10^-15 with 1024 ports. Experimental 10 Gb/s operation using optical fiber delay lines with gate control circuits shows that the bit error rate of the buffer is less than 10^-12     

Optical TDM sorting networks for high-speed switching

The general time-space-time switching problem in telecommunications requires the use of multichannel time slot interchangers. We propose two multichannel time slot sorters which sort N² time-division multiplexed (TDM) optical inputs, arranged as N frames with N time slots per frame using O(Nlog²N) optical switch elements. The TDM optical inputs are sorted in place without expanding the space-time fabric into a space-division switch. The hardware components used are 2×2 optical switches (LiNbO₃ directional couplers) and optical delay lines connected in a feedforward fashion. Two space-time variants of the spatial odd-even merge algorithm are used to design the sorters. By maintaining the number of shift-exchange operations invariant at each stage, the proposed sorters use fewer switches than previously proposed sorters using switches with feedback line delays. The use of local control at each 2×2 switch makes the proposed sorters more practical for high-speed optical inputs than Benes-based time slot permuters with global control and high latency, which affects interframe distance. Both time slot sorters support pipelining of input frames and sorted outputs are available at each time slot after an initial frame delay. The proposed sorters find practical application in the time-domain equivalents of space-division, nonblocking, self-routing packet switches using the sort-banyan architecture, such as the Starlite switch, Sunshine switch, etc     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

Physical performance limits for shared buffer ATM switches

Performance studies, linking ATM switch capabilities to physical limitations imposed by integrated circuit technology, have been scarce. This paper explores trends in circuit capabilities, and makes projections toward the 0.25-μm technologies that will be available to all switch designers in the year 2000. The limits imposed by circuit technology are applied to shared buffer ATM switches. We determine requirements and physical limits for buffer capacity, buffer throughput, chip I/O throughput, and power dissipation. As a result, we are able to project chip counts, aggregate switch throughputs, and switch dimensions. As well, performance capabilities of single-chip shared buffer switches are estimated. A single-chip shared buffer switch implemented in 0.25-μm technology will be capable of an aggregate throughput of 1.3 Tb/s, will accomplish almost arbitrarily low cell loss rates for bursty traffic, and may be integrated together with translation tables supporting hundreds of connections per port     

Optical self-routing switch using integrated laser diode opticalswitch

A 2×2 optical self-routing switch using integrated laser diode optical switches is proposed. The switch is composed of a Benes network, which can perform large-scale switching functions using less hardware than a crossbar switch. The path each data stream takes through the interconnection network is determined by the binary bits of its destination address, and self-routing is accomplished by monitoring terminal voltage changes in gain guides induced by input optical signals which are injected into a p-n junction. Concentrated control is not necessary, and large optical multistage switches can be easily constructed because complicated electrode patterns are not necessary     

A smart photonic ATM switch architecture with compression strategy

Generally, the limitations of optical delay line and link capacity limit the switching efficiency in the photonic asynchronous transfer mode (ATM) switch. Under the constraints, a smart photonic ATM switch designed for high-speed optical backbone network should have some fast switching strategies so that the congestion can be avoided or reduced. In this paper, we mill propose a novel smart photonic ATM switch architecture with a novel compression strategy. In the smart architecture, while more than two frames are destined for the same destination, the losers will be queued and compressed to reduce the degree of congestion. Therefore, not only the total switching time (TST) can be reduced but also the scarce buffer is able to store more incoming cells. To meet the high-speed switching performance, a simple and efficient compression decision algorithm (CDA) is proposed. The timing of employing compression strategy and the saturated performance of proposed strategy are analyzed. Simulation results show that compared to the conventional photonic ATM switch without compression strategy, the proposed strategy offers a much better performance in terms of queueing delay     

An optical packet switch based on WDM technologies

Dense wavelength-division multiplexing (DWDM) technology offers tremendous transmission capacity in optical fiber communications. However, switching and routing capacity lags behind the transmission capacity, since most of today's packet switches and routers are implemented using slower electronic components. Optical packet switches are one of the potential candidates to improve switching capacity to be comparable with optical transmission capacity. In this paper, we present an optically transparent asynchronous transfer mode (OPATM) switch that consists of a photonic front-end processor and a WDM switching fabric. A WDM loop memory is deployed as a multiported shared memory in the switching fabric. The photonic front-end processor performs the cell delineation, VPI/VCI overwriting, and cell synchronization functions in the optical domain under the control of electronic signals. The WDM switching fabric stores and forwards cells from each input port to one or more specific output ports determined by the electronic route controller. We have demonstrated with experiments the functions and capabilities of the front-end processor and the switching fabric at the header-processing rate of 2.5 Gb/s. Other than ATM, the switching architecture can be easily modified to apply to other types of fixed-length payload formats with different bit rates. Using this kind of photonic switch to route information, an optical network has the advantages of bit rate, wavelength, and signal-format transparencies. Within the transparency distance, the network is capable of handling a widely heterogeneous mix of traffic, including even analog signals.     

Large-scale ATM multistage switching network with shared buffermemory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed     

新型光缓存器和2×622Mb／s ATM光交换系统

本文给出一种新型的光缓存器的结构，以解决在ＡＴＭ光交换中的信元碰撞问题。这种缓存器由光纤延迟线、光波导开关阵及非线性半导体光放大器构成。文中还报告了一种用于交换各用户不同速率的信元（可达６２２Ｍｂ／ｓ）的ＡＴＭ光交换实验系统，系统的总容量为１．２Ｇｂ／ｓ。     

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

Design and architecture of a new space priority mechanism for ATM network nodes

This paper presents the architecture of a new space priority mechanism intended to control cell loss in ATM switches. Our mechanism is a new generic concept called: the multiple pushout. It is based on the utilization of both AAL and ATM features and on a particular definition of the priority bit. Whenever one cell of a message overflows the buffer of an ATM switch, the algorithm causes the switch to discard other cells of the message (including later arrivals). Such discarding frees buffer spaces for cells of other messages that have a chance of arriving at their destination intact. Our objective is to emphasize that in case of overload, with most of proposed mechanisms, cells are discarded without any semantic information about the type of cells. Therefore, at the destination, all the fragments of the corrupted messages will be discarded anyway. Finally, we present simulation results comparing cell loss rates and message loss rates of several space priority mechanisms.     

An ultrafast photonic ATM switch based on bit-interleavemultiplexing

An optical ATM switch is proposed in which cells from individual input channels are time-division multiplexed in a bit-interleave manner. This switch can easily handle multicast switching because it is based on a broadcast-and-select network. Compared to an alternative switch that uses a cell-interleave time-division multiplexing scheme, the proposed optical switch has a much simpler structure. It does not need a cell compressor at each input and a cell expander at each output, which greatly reduces hardware complexity. Feasibility analyzes showed that a 64×64 photonic ATM switch with 2.5 Gb/s input/output is possible using the proposed technology. In an experimental demonstration, 4 b cells were selected from a 55 Gb/s bit-interleave multiplexed cell stream by using a new nonlinear optical fiber switch. With its high switch throughput, our switch is a strong candidate for future large-capacity optical switching nodes     

Self-routing planar network for guided-wave optical switching systems

An N*N self-routing planar network suitable for fabricating optical space switches on lithium niobate substrate is presented. The network has O(N/sup 2/) cross points, good modularity and expandability. It also has no waveguide crossovers and no differential attenuation between any of the input and output pairs. A self-routing control can be applied to this network, which is indispensable for ATM switching systems.<>