A content addressable memory with a fault-tolerance mechanism

The use of a latch-based fault-tolerance mechanism is described in the design of a word-parallel content-addressable memory, using test circuitry and addressing mechanisms which are already in place at a cost of only a 4% increase in the word area.     

Novel content addressable memory

The design and performance of a content addressable memory (CAM) LSI using a newly developed cell circuit is presented. The LSI has all the functions necessary to implement a high-speed data searching system and is fabricated using a 3 mu m CMOS double-metallisation process. A cycle time of 60 ns with the basic associative operation taking 20 ns has been measured.<>     

A content addressable memory using Josephson junctions

A content-addressable memory circuit using Josephson nondestructive readout (NDRO) memory cells is described. The memory circuit proposed performs searching functions, such as coincidence, incoincidence, and don't-care functions, in addition to the conventional memory function of writing and reading. This memory circuit is able to achieve the `less than' function in addition to the three functions listed above. Computer simulation of a 3-word by 3-b memory was used to investigate how high-performance operation can be achieved. The simulation results show that the four operations for all combinations of binary inputs have been achieved with a cycle time of less than 80 ps and a 0.28-μW/cell dissipation. The simulation results also show the design tolerances of the gate currents of four superconducting quantum interference device (SQUID) gates used in the memory circuit to range from 25% to 17%     

A boolean content addressable memory and its applications

A memory called the Boolean Content Addressable Memory integrates the content-based address identification logic into the RAM comprising 1-bit words. This memory is suitable for on-chip VLSI implementation and compatible with the RAM for on-board implementation. Its application includes list management and graph traversal.     

A content addressable distributed logic memory with applications to information retrieval

This paper describes a content addressable memory system in which logic is distributed throughout the system. The memory is made up of cells. Each cell is a small finite-state machine which can communicate with its neighbors. These cells are controlled through a set of programming commands. The application of this memory to several problems related to information retrieval is discussed.     

A special-purpose content addressable memory chip for real-timeimage processing

An application specific integrated circuit (ASIC) using a special-purpose content addressable memory that performs parallel search and multiple update (PSMU) operation is presented. This chip, referred to as multiple update content addressable memory (MUCAM), can search 256, 8-b-wide locations in parallel for target data and update all such locations with new data within 50 ns. MUCAM has been developed for image component labeling and merging operation in a connected component analyzer. It was fabricated using 0.9-μm CMOS technology     

An on-chip electroosmotic micropump with a light- addressable potentiometric sensor

An on-chip electroosmotic (EO) micropump (EOP) was integrated in a microfluidic channel combined with a light-addressable potentiometric sensor (LAPS). The movement of EO flow towards right and left directions can be clearly observed in the microfluidic channel. The characteristics of photocurrent-time and photocurrent-bias voltage are obtained when buffer solution passes through the sensing region. The results demonstrate that the combination of an on-chip EOP with an LAPS is feasible.     

Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays

The design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays is described. The proposed cell is capable of storing three internal states: ONE, ZERO, and `don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-/spl mu/m design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25/spl times/22 /spl mu/m/SUP 2/, which is comparable to 64-kb static random access memory (RAM) cell areas. The CAM cell was successfully fabricated using a 4-/spl mu/m NMOS process and its operation was verified with a 2/spl times/3-bit array.     

A ternary content addressable search engine

The design, implementation, and experimental results for a ternary content addressable search engine chip, known as the Database Accelerator (DBA), are discussed. The DBA chip architecture is presented. It is well suited to serve as a coprocessor for a variety of logic search applications. The core of the DBA system is composed of novel high-density content addressable memory (CAM) cells capable of storing three states. The design of these cells and their support circuitry are described. The CAM cell and support circuitry were fabricated and their operation confirmed. The circuit implementation of the DMA data path is described with particular emphasis on the optimization of the multiple response resolver. The timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, are reported. Experimental DBA chip results that verify the full functionality and testability of the design are presented     

Low-power content addressable memory design using two-layer P-N match-line control and sensing

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs.     

Immediate soft error detection using pass gate logic for content addressable memory

Content addressable memory (CAM) is used in many applications. As the process technology scales into the deep sub-micron regime, soft error rate increases significantly. Densely integrated memory cells in CAM are prone to soft errors. Bit flipping in CAM leads to an incorrect search operation which could be fatal from a system point of view. The proposed scheme enables the detection of soft errors immediately and the correction of problems with small additional logic gates.     

降低亚100nm CAM电路的软错误易感性

电路的软错误易感性是VLSI设计中需要考虑的重要问题。CAM广泛应用于各种片上结构中,非常容易受软错误感染。然而,CAM的保护比其它存储元件难度更大。本文首先研究了软错误对不同类型、不同特征尺寸CAM的影响。在介绍一种软错误免疫CAM单元SSB-RCAM后,提出两种可靠CAM DCF-RCAM和DCK-RCAM。此外,本文还提出一种抛弃机制保护双单元冗余CAM免受软错误的影响。实验结果表明,11T-NOR结构的CAM单元在软错误免疫性上具有优势。基于11T-NOR结构,所提出的可靠CAM结构在可接受的开销下,平均可降低约81%的软错误率。在特定的应用中,还可以通过使用抛弃机制降低双单元冗余CAM的软错误率。     

Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits

We first study the impacts of soft errors on various types of CAM for different feature sizes. After presenting a soft error immune CAM cell, SSB-RCAM, we propose two kinds of reliable CAM, DCF-RCAM and DCK-RCAM.In addition, we present an ignore mechanism to protect dual cell redundancy CAMs against soft errors. Experimental results indicate that the 11T-NOR CAM cell has an advantage in soft error immunity. Based on 11T-NOR, the proposed reliable CAMs reduce the SER by about 81% on average with acceptable overheads. The SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.     

Testing content addressable memories with physical fault models

Content addressable memory （CAM） is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N＋2L＋4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N＋2L＋5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.     

Testing content addressable memories with physical fault models

the effectiveness and efficiency of the proposed physical fault models and algorithms.     

A CCD line addressable random-access memory (LARAM)

A novel approach to charge-coupled device (CCD) memory organization has been conceived and implemented in a 16 384-bit memory chip. It utilizes an isoplanar n-channel silicon gate MOS process in conjunction with self-aligned implanted barrier, buried channel CCD technology. The chip is organized in four parallel, identical sections of 32 independent lines with each line 128 bits long. The four sections are controlled in parallel. Any of the 32 lines (the same line in each of the four sections) can be randomly accessed; hence the name, line addressable random-access memory (LARAM). Each line can be brought to a halt at any of its 128 possible positions. Design features and test results of the memory are described.     

A 6-ns cycle 256-kb cache memory and memory management unit

A 6-ns cycle, 7.7-ns access cache memory and memory management unit (CAMMU) chip has been developed. The circuit includes two 5-ns 128-kb cache memories, two 4-ns 64-entry fully associative translation lookaside buffers (TLBs), two 4-ns 64-line tag RAMs, comparators, registers, and control logic. The TLB design contains a line encoder and valid bits with flash clear. Timing control allows read, write, associative accesses, and invalid search accesses with identical timings. The two caches time-share data input and sense amplifier circuits for improved density, and they are pipelined to allow a new access to start before the previous access is complete     

8192-bit block addressable CCD memory

Design data and experimental characteristics are given on an 8192-bit n-channel charge-coupled memory device, intended for applications requiring shorter latency than ordinary MOS shift registers or fixed-head disks and at potentially lower cost than either MOS shift registers or random-access memories. This was achieved by dividing the array into 32 memory blocks of 256 bits each, with addressable, random access to any block, permitting average latency of approximately 100 /spl mu/s. A two-level overlapping polysilicon gate process was used, with conservative design tolerances. Power dissipation on-chip, plus capacitive drive power during data access at 1 MHz is approximately 250 mW, and less than 5 mW during standby at 20 kHz with data retention.