Novel content addressable memory

The design and performance of a content addressable memory (CAM) LSI using a newly developed cell circuit is presented. The LSI has all the functions necessary to implement a high-speed data searching system and is fabricated using a 3 mu m CMOS double-metallisation process. A cycle time of 60 ns with the basic associative operation taking 20 ns has been measured.<>     

A content addressable memory with a fault-tolerance mechanism

The use of a latch-based fault-tolerance mechanism is described in the design of a word-parallel content-addressable memory, using test circuitry and addressing mechanisms which are already in place at a cost of only a 4% increase in the word area.     

A content addressable memory using Josephson junctions

A content-addressable memory circuit using Josephson nondestructive readout (NDRO) memory cells is described. The memory circuit proposed performs searching functions, such as coincidence, incoincidence, and don't-care functions, in addition to the conventional memory function of writing and reading. This memory circuit is able to achieve the `less than' function in addition to the three functions listed above. Computer simulation of a 3-word by 3-b memory was used to investigate how high-performance operation can be achieved. The simulation results show that the four operations for all combinations of binary inputs have been achieved with a cycle time of less than 80 ps and a 0.28-μW/cell dissipation. The simulation results also show the design tolerances of the gate currents of four superconducting quantum interference device (SQUID) gates used in the memory circuit to range from 25% to 17%     

A boolean content addressable memory and its applications

A memory called the Boolean Content Addressable Memory integrates the content-based address identification logic into the RAM comprising 1-bit words. This memory is suitable for on-chip VLSI implementation and compatible with the RAM for on-board implementation. Its application includes list management and graph traversal.     

A content addressable distributed logic memory with applications to information retrieval

This paper describes a content addressable memory system in which logic is distributed throughout the system. The memory is made up of cells. Each cell is a small finite-state machine which can communicate with its neighbors. These cells are controlled through a set of programming commands. The application of this memory to several problems related to information retrieval is discussed.     

A special-purpose content addressable memory chip for real-timeimage processing

An application specific integrated circuit (ASIC) using a special-purpose content addressable memory that performs parallel search and multiple update (PSMU) operation is presented. This chip, referred to as multiple update content addressable memory (MUCAM), can search 256, 8-b-wide locations in parallel for target data and update all such locations with new data within 50 ns. MUCAM has been developed for image component labeling and merging operation in a connected component analyzer. It was fabricated using 0.9-μm CMOS technology     

Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays

The design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays is described. The proposed cell is capable of storing three internal states: ONE, ZERO, and `don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-/spl mu/m design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25/spl times/22 /spl mu/m/SUP 2/, which is comparable to 64-kb static random access memory (RAM) cell areas. The CAM cell was successfully fabricated using a 4-/spl mu/m NMOS process and its operation was verified with a 2/spl times/3-bit array.     

A ternary content addressable search engine

The design, implementation, and experimental results for a ternary content addressable search engine chip, known as the Database Accelerator (DBA), are discussed. The DBA chip architecture is presented. It is well suited to serve as a coprocessor for a variety of logic search applications. The core of the DBA system is composed of novel high-density content addressable memory (CAM) cells capable of storing three states. The design of these cells and their support circuitry are described. The CAM cell and support circuitry were fabricated and their operation confirmed. The circuit implementation of the DMA data path is described with particular emphasis on the optimization of the multiple response resolver. The timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, are reported. Experimental DBA chip results that verify the full functionality and testability of the design are presented     

Immediate soft error detection using pass gate logic for content addressable memory

Content addressable memory (CAM) is used in many applications. As the process technology scales into the deep sub-micron regime, soft error rate increases significantly. Densely integrated memory cells in CAM are prone to soft errors. Bit flipping in CAM leads to an incorrect search operation which could be fatal from a system point of view. The proposed scheme enables the detection of soft errors immediately and the correction of problems with small additional logic gates.     

A CCD line addressable random-access memory (LARAM)

A novel approach to charge-coupled device (CCD) memory organization has been conceived and implemented in a 16 384-bit memory chip. It utilizes an isoplanar n-channel silicon gate MOS process in conjunction with self-aligned implanted barrier, buried channel CCD technology. The chip is organized in four parallel, identical sections of 32 independent lines with each line 128 bits long. The four sections are controlled in parallel. Any of the 32 lines (the same line in each of the four sections) can be randomly accessed; hence the name, line addressable random-access memory (LARAM). Each line can be brought to a halt at any of its 128 possible positions. Design features and test results of the memory are described.     

A 6-ns cycle 256-kb cache memory and memory management unit

A 6-ns cycle, 7.7-ns access cache memory and memory management unit (CAMMU) chip has been developed. The circuit includes two 5-ns 128-kb cache memories, two 4-ns 64-entry fully associative translation lookaside buffers (TLBs), two 4-ns 64-line tag RAMs, comparators, registers, and control logic. The TLB design contains a line encoder and valid bits with flash clear. Timing control allows read, write, associative accesses, and invalid search accesses with identical timings. The two caches time-share data input and sense amplifier circuits for improved density, and they are pipelined to allow a new access to start before the previous access is complete     

8192-bit block addressable CCD memory

Design data and experimental characteristics are given on an 8192-bit n-channel charge-coupled memory device, intended for applications requiring shorter latency than ordinary MOS shift registers or fixed-head disks and at potentially lower cost than either MOS shift registers or random-access memories. This was achieved by dividing the array into 32 memory blocks of 256 bits each, with addressable, random access to any block, permitting average latency of approximately 100 /spl mu/s. A two-level overlapping polysilicon gate process was used, with conservative design tolerances. Power dissipation on-chip, plus capacitive drive power during data access at 1 MHz is approximately 250 mW, and less than 5 mW during standby at 20 kHz with data retention.     

An innovative design of spin transfer torque based ternary content addressable memory with match line sense amplifier

Ternary Content Addressable Memory (TCAM) device is integrated with Static-Random Access Memory unit to attain high production at a lesser cost. Moreover, the TCAM searching device performs faster parallel searching of whole memory in the entire time. Also, TCAM is constrained by its large area of the cell, extensive active state leakage current, and high power consumption for searching. In this present work, an innovative Spin Transfer Torque-TCAM (STT-TCAM) with Match Line Sensing Amplifier sensing scheme is developed to acquire trustworthy sensing functions with high speed. The projected scheme has pertained minimum consumption of power and high operating speed. The proposed method consumes a lesser amount of power and functions at a higher speed. It also exploits the least number of resources compared to the prevailing techniques. The proposed designing is done with the use of Xilinx vertex 6 simulation tools and it calculated the power, current, voltage, frequency and delay values used in this simulation. Hence, the attained parameters are compared with recent existing methods to prove the efficacy of the proposed TCAM model.

     

Decoupled dynamic ternary content addressable memories

The content addressable memory (CAM) is a memory in which data can be accessed on the basis of contents rather than by specifying physical address. In the paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A ternary CAM cell is capable of storing and matching three values: zero (0), one (1), and don't care (X). The proposed dynamic CAM (DCAM) cells range in the number of transistors from 6 n-type transistors up to 10.5 n- and p-type transistors (one transistor is shared between two cells). The cells are capable of fast match and read operations enhancing the performance of the memory system. Using a 0.25-/spl mu/m CMOS technology, simulations of the proposed CAM cells were performed to compare their performance. With this technology, the shortest match delay is 89.7 ps for the 7.5 DCAM cell. A complete characterization of the five cells is provided in this paper. These results show that the novel CAM cells outperform existing cells. The compact size and low power dissipation of these ternary CAM cells make them suitable for many applications such as routers, database, and associative cache memories.     

微处理器中存储器管理的研究

通过分析该微处理器访存的时序要求以及对存储器保护的要求,设计了具有自主知识产权的存储器管理部件,论述了逻辑地址映射到物理地址、存储块保护以及Cache设计思想.     

A user's guide to non-volatile, on-chip analogue memory

On-chip, non-volatile analogue memory is essential in hardware implementations of many of the early stages of signal processing, including neural network preprocessors and other adaptive sensor fusion amplifiers. Such storage is also desirable for trimming analogue circuits electronically and for parameter retention on power-down. This paper reviews the current state-of-the-art from a designer's perspective, highlighting the promises and problems associated with a range of approaches     

An improved field-controlled polarization-transfer device and the operating features of the exploratory content addressable memory system

A new type of ferroelectric which exhibits a threshold switching field and a number of highly useful technical properties is simply distinguished from ordinary ferroelectrics as ferrielectrics. These new materials have been described in detail in various publications. The good industrial properties of the mixed bismuth oxide (MBO) ferrielectrics permitted the extension of work on fundamental research into applied research. The objective of this work was to demonstrate that capacitor elements comprised of MBO-type ferrielectrics exhibiting a threshold field as a dielectric represent an important improvement as compared to ordinary ferroelectric capacitors, and they can be utilized as logic and memory devices. Work was essentially devoted to the following application areas. 1) Improved field controlled polarization transfer devices (Transpolarizers ®) were developed. These transpolarizers utilize internally biased MBO-type ferrielectrics which made it possible to block and unblock the transpolarizer with opposite polarity pulses. Furthermore two-section transpolarizers requiring only ten volts for switching have been fabricated. Due to the improved switching features and low switching levels attained, these transpolarizers are compatible with transistor technology. 2) An exploratory content addressable memory system using these improved transpolarizers was developed and constructed, and its operating features are described.     

A fast on-chip profiler memory using a pipelined binary tree

We introduce a novel memory architecture that can count the occurrences of patterns on a system's bus, a task known as profiling. Such profiling can serve a variety of purposes, like detecting a microprocessor's software hot spots or frequently used data values, which can be used to optimize various aspects of the system. The memory, which we call ProMem, is based on a pipelined binary search tree structure, yielding several beneficial features, including nonintrusiveness, accurate counts, excellent size and power efficiency, very fast access times, and the use of standard memories with only simple additional logic. The main limitation is that the set of potential patterns must be preloaded into the memory. We describe the ProMem architecture, and show excellent size and performance advantages compared with content-addressable memory (CAM) based designs.