An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design     

InP DHBT-based distributed amplifier for 100 Gbit/s modulator driver operation

A distributed amplifier for use as a modulator driver in next generation optical data communication systems has been manufactured using InP double-hetero bipolar transistor (DHBT) technology with an emitter size of 0.7 times 1 mum². The amplifier achieved a gain of 21 dB and a 3 dB bandwidth of 120 GHz, resulting in a gain-bandwidth product of 1.35 THz. Clearly open 100 Gbit/s 231/1 non-return-to-zero pseudorandom bit sequence (NRZ PRBS) eye diagrams with an output voltage swing of 2.3 V have been measured.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n+-InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n+-InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n+-InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

Simulated study on the InP/InGaAs DHBT under proton irradiation

A 3D model simulation of InP/InGaAs/InP DHBT is reported in this paper. A comprehensive set of built-in physical models are described, including Stratton''s hydrodynamic model, high-fields mobility model and thermionic emission model. A mixed-mode environment is required for AC simulation instead of simulating an isolated HBT, in which the HBT is embedded in an external circuit, and the circuit voltage and current equations are solved along with the Poisson equation and transport equations. In AC simulation, simulator Sentaurus provides the computation of the small signal admittance Y matrix. From the results of Y matrix, the small signal equivalent circuit is constructed with the conductance and capacitance obtained from Y matrix, and the AC parameters, such as S-parameters, will be calculated. The small signal AC characteristics of InP/InGaAs DHBTs under proton irradiation are simulated with different fluences of proton irradiation. Simulation results show that the maximum oscillation frequency will be degraded when fluence of proton irradiation is increased.     

InP DHBT selector-driver with 2 X 2.7 V swing for 100 Gbit/s operation

An integrated selector-driver is designed for 100 Gbit/s operation and fabricated using 0.7 μm InP double-heterojunction bipolar transistor (DHBT) technology. The driver has a lumped architecture and operates in differential mode. Two complementary signals each with 2.7 V amplitude (3.2 V_{pp) have been measured at 100 Gbit/s.}     

Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses

We report on the reliability of InGaAs/InP DHBT technology which has applications in very high-speed ICs (over 100 Gbits/s). This work presents the results of accelerated aging tests under thermal and electrical stresses performed on HBT up to 2000 h. Stress conditions consist in applying collector–emitter bias V_CE from 1.3 to 2.7 V and collector current densities J_C of 400 and 610 kA/cm². The corresponding junction temperatures T_J extends from 83 to 137 °C. The base current ideality factor η_B increase and the current gain β decrease have revealed a degradation of the base–emitter junction. The normalized current gain β_norm drop has occurred earlier for higher V_CE and/or higher T_J. A 20% decrease of β_norm chosen as the failure criterion leads to an activation energy of 1.1 eV.     

Evaluation of encapsulation and passivation of InGaAs/InP DHBT devices for long-term reliability

Device encapsulation and passivation are critical for long-term reliability and stability. Several encapsulation techniques were evaluated in terms of degradation of electrical characteristics, gap filling under the mesa structures, and adhesion to the semiconductor and metal surfaces. These included plasma enhanced chemical vapor deposited (PECVD) SiO₂, electron cyclotron resonance CVD SiN_x, spin-on glass, benzocyclobutene, and polyimide. Damage from plasma exposure caused gain degradation in the devices. Spin-on coatings cause little to no gain degradation, provided that there is minimal stress in the cured film. SOG and BCB films have acceptable adhesion properties and were excellent for gap filling. Polyimide films have excellent adhesion properties, however, they were poor at gap filling and had a great deal of shrinkage during curing. Device passivation was evaluated using double heterojunction bipolar transistor structures with either an abrupt or graded emitter-base junction. Abrupt junction devices had the self-aligned base metal directly on the p⁺ InGaAs base. Graded junction devices had the base metal on top of graded InGaAsP layers, which the metal was diffused through, to make contact to the base region. Abrupt junction devices stressed at an initial J_E of 90 kA/cm² at a V_CE of 2V at 25°C degraded 20% within 70 h of operation, whereas, the graded junction devices show no degradation in dc characteristics after operation for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

We report on the reliability of InP HBT technology which has applications in very high-speed ICs. This work presents the storage accelerated aging tests results performed on InP/InGaAs HBT at stress temperatures of 180, 210 and 240 °C up to 3000 h. We have performed aging tests for two generations of InP HBT which differ from the collector doping level and from material used for planarization. From the Gummel plots, we note that the major degradation mechanism is located at the base–emitter junction periphery. Investigations on the physical origin of the observed failure mechanism has been performed using TCAD simulations.     

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

带有阶梯缓变集电区的InP/InGaAs/InP DHBT材料研究

设计并生长了一种新的InP/InGaAs/InP DHBT结构材料,采用在基区和集电区之间插入两层不同禁带宽度的InGaAsP四元系材料的阶梯缓变集电结结构,以解决InP/InGaAs/InP DHBT集电结导带尖峰的电子阻挡效应问题。采用气态源分子束外延(GSMBE)技术,通过优化生长条件,获得了高质量的InP、InGaAs以及与InP晶格相匹配的不同禁带宽度的InGaAsP外延材料。在此基础上,成功地生长出带有阶梯缓变集电区结构的InP基DHBT结构材料。     

160-Gbit/s clock recovery using an electro-absorption modulator and 40-Gbit/s ETDM demultiplexer

A 10-GHz clock recovery from a 16×10-Gbit/s optical time-division-multiplexed (OTDM) data stream is experimentally demonstrated using an electro-absorption modulator and 40-Gbit/s electric time-division-multiplexed (ETDM) demultiplexer. The recovered clock signal exhibits excellent stability, with root square (RMS) jitter of 328 and 345 fs corresponding to back-to-back and transmission over 100 km, respectively.     

High-frequency InGaAs/InP multiple-quantum-well buried-mesa electroabsorption optical modulator

We describe the structure and performance characteristics of an InGaAs/InP multiple-quantum-well (MQW) electro-absorption buried-mesa optical modulator. The device is fabricated with two metal-organic chemical-vapour-deposition (MOCVD) growth steps, wherein small-area circular (40?m diameter) PIN diodes are buried with Fe-doped semiinsulating (SI) InP regrowth. The modulator has a relatively low insertion loss (4.5 dB) with 25% modulation depth and very high modulation bandwith (5.3 GHz) operating at 1.62?m wavelength.     

0.1-42 GHz InP DHBT distributed amplifiers with 35 dB gain and 15 dBm output

An InP double hetero-junction bipolar transistor (DHBT) distributed power amplifier MMIC with 35 dB gain, 42 GHz bandwidth and 15 dBm output power is reported. This represents the highest power and largest gain reported over this bandwidth from a single chip HBT amplifier. A lumped preamplifier with a novel distributed output is used to obtain high gain and wide bandwidth at these power levels.     

Dry-etch fabrication of reduced area InGaAs/InP DHBT devices for high speed circuit applications

We have fabricated reduced area InGaAs/InP DHBTs for high speed circuit applications. To produce the small dimensions required, a process involving both wet chemical and ECR plasma etching was developed. Optical emission spectroscopy was used for end-point detection during plasma etching. With this improved process, an f_t of 170 and f_max of 200 GHz were achieved for 1.2 × 3 μm² emitter size devices with a 500 ? base.     

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm⁻² and a collector bias, V_CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

InGaAs/InP DHBT technology and design methodology for over 40 Gb/soptical communication circuits

High-performance technologies and adequate design methodologies are required to address the needs of very high-speed ICs (VHSICs) for over 40 Gb/s optical communications. We describe improvements we have introduced in our InP DHBT technology, and how our design methodology has evolved, we show how it results in improved circuit designs, and present some recent results, with some considerations on measurement limitations