一种高线性度宽带射频放大器

采用InGaP HBT工艺,结合达林顿放大器技术,制作了一种高线性度宽带射频放大器。与传统结构相比,该射频放大器具有高线性度、宽带宽的优点。在10 MHz~1 GHz的频率范围内,该放大器的输出1 dB压缩点达到21.8 dBm,输出3阶交调截止点达到40.6 dBm,两者差值为18.8 dBm。而传统射频放大器的输出3阶交调截止点仅比输出1 dB压缩点高出10 dBm。这表明,该放大器非常适合应用于大动态信号处理系统。     

CMOS全差分超宽带低噪声放大器

文中给出了一个应用于超宽带射频接收机中的全集成低噪声放大器,该低噪声放大器采用了电阻并联负反馈与源极退化电感技术的结合,为全差分结构,在Jazz0.18μm RF CMOS工艺下实现,芯片面积为1.08mm2,射频端ESD抗击穿电压为1.4kV。测试结果表明,在1.8V电源电压下,该LNA的工作频带为3.1～4.7GHz,功耗为14.9mW,噪声系数(NF)为1.91～3.24dB,输入三阶交调量(IIP3)为-8dBm。     

无线应用中的低噪声放大器设计与分析

低噪声放大器在接收系统中能降低系统的噪声和提高接收机灵敏度,是接收系统的关键部件.描述了一种用于无线通信射频(RF)前端的低噪声放大器(LNA)的设计,先总体阐述了低噪声放大器的主要技术和性能指标,然后在采用ATF34143微波晶体管的基础上,依据低噪声放大器的各项指标来同步进行电路的设计、优化和ADS仿真,结果表明设计的低噪声放大器完全满足性能指标要求,其功率增益可达16dB,噪声系数(NF)在0.5dB以下.     

产品

通用IC ADI推出RF驱动放大器ADL5321 ADI公司推出ADL5321高性能、低功耗RF驱动放大器,适合用于LTE、WiMAX与WiBro的2.3 GHz～4.0 GHz无线基础设施设计。在2600 MHz时,ADL5321的三阶输出交调截点(OIP3)为40 dBm,输出压缩点为25 dBm,对于指定的发射输出功率而     

一款低噪声卫星导航接收机射频前端的设计

基于0.18tm RF CMOS工艺,采用低中频系统结构,设计了一款可应用于全球定位导航系统(GPS) L1频段和北斗二代(BD2) B1频段的低噪声卫星导航接收机的射频模拟前端芯片.该前端包括低噪声放大器、无源混频器、中频放大器、复数带通滤波器和数控可变增益放大器.其中低噪声放大器采用电流舵技术,与无源混频器一起,提高了射频前端的1 dB压缩点输入功率(Pi(1dB)),有效地改善了系统的线性度.测试结果显示,在GPS L1频点,系统的最大增益107.2 dB,噪声系数达到1.8 dB,动态增益66 dB,镜像抑制比约为39.54 dB,Pi(1dB)为-41 dBm,电源为1.8V时,消耗电流16 mA,芯片面积1.7 mm×0.8 mm.     

高线性低噪声放大器设计

介绍一种L波段单级高线性低噪声放大器的工作原理和设计方法。与传统的接收机射频前端放大器主要考虑低噪声和高增益特性不同，文中选用了低成本、低功耗的SiGe NPN BJT器件设计高三阶交截点的低噪声放大器。设计中利用了微波CAD工具对电路进行仿真与优化，同时对生成的微带印刷电路板进行了电磁仿真。     

一种高性能宽带直接变频射频前端设计

提出一种宽带(250 MHz~4.7 GHz)无电感BiCMOS射频前端结构,包含低噪声跨导放大器(LNTA)、带电阻无源混频器和跨阻级。低噪声跨导放大器使用了噪声和线性度消除技术,例如输入交叉耦合结构、互补输入和电流复用技术。带电阻无源混频器采用退化电阻来提高线性度。仿真结果表明, 当电源电压为3.3 V时,总电流为9.38 mA, 噪声系数为9.8 dB(SSB),电压转换增益为20 dB,输入3阶交调为+11.8 dBm。     

一种L频段高线性度低噪声放大器的设计

对低噪声放大器线性度提高的方法进行分析。基于导数交叠法,使两个晶体管偏置在不同区域,并利用这两个晶体管源端产生的相位差,抵消了3阶项电流。采用TSMC 90 nm CMOS 工艺,实现了一款L频段高线性度全差分低噪声放大器,测试得到输出3阶交调点达30.6 dBm,增益为14.54 dB,噪声系数为1.63 dB,功耗为45 mA@3.3 V。     

移动通信400MHz—2.5GHz低噪声下变频混频器

在便携式通信设备(如蜂蜂窝电话和数字无绳电话)中,需要各类低噪声混频器,用于频率变换。如图1所示的GSM移动通信射频接收模块,它就包括了高频低噪声混频器。混频器是具有混频作用的非线性器件,它利用器件的非线性特性将输入射频信号(RF)与本振信号(LO)两个不     

适合于多吉赫兹应用的0.5 V CMOS cascode低噪声放大器设计

本文介绍了适用于低功耗无线通信的0.5 V 多吉赫兹CMOS cascode 低噪声放大器设计。通过对传统cascode结构进行直流分离,去除了因堆积MOS管导致的工作电压限制。同时,采用正向体偏置技术,cascode结构低噪声放大器能工作在0.5 V供电电压。文章研究了电路设计细节和射频性能。为验证研究结果,采用台积电0.18微米射频工艺的0.5 V 5.4吉赫兹低噪声放大器被设计,制造出来并进行了测量。测量结果表明,该低噪声放大器在0.5 V工作电压下工作电流为5毫安,其增益为9.1分贝,噪声系数为3分贝,输入三阶交调点为-3.5 分贝毫瓦。通过和那些已发表的cascode低噪声放大器比较,本文的低噪声放大器具有工作电压低,功耗低而射频性能相当的特点。     

Effect of collector bias current on the linearity of common-emitter BJT amplifiers

Using a Volterra series,an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current(I_(CQ)) in a common-emitter bipolar junction transistor amplifier.The analysis indicates that the larger I_(CQ) is,the more linear the amplifier is.Furthermore,this has been verified by experiment.This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA(low noise amplifier) as an application of the analysis result obt...     

Low-distortion downconvertor using varactor diodes

A balanced varactor downconvertor for a 6.8 GHz input signal is described. Measured intermodulation and conversion performance are given. Compared to Schottky-diode mixers this downconvertor has a considerably higher 3rd-order intercept point.     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

一种应用于DRM/DAB/DVB-H的噪声抵消和IP3改进的CMOS射频前端设计

本文给出了一种应用于数字广播标准的CMOS射频前端电路芯片,其包括宽带低噪声放大器、正交混频器和可变增益放大器,该前端能够支持200kHz-2GHz频率范围内的多种无线通信标准,该电路在没有牺牲其他电路性能包括电压增益和功耗的情况下,改善了NF和IP3。通过噪声抵消技术降低前端的NF,通过差分多栅晶体管结构（DMGTR）提高前端的IP3。dB线性可变增益放大器的增益控制通过采用工作在线性区的PMOS晶体管来实现。芯片采用0.18um CMOS工艺实现。测试结果表明在200kHz-2GHz范围内S11小于-11.4,增益变化范围在250MHz为12-42dB,在2GHz为4-36dB。单边带NF为3.1-6.1 dB。在中等增益情况下IIP3为-4.7-2.0dBm。整个前端在1.8V电源电压情况下功耗仅仅为36mW。     

Magnetic-Feedback-Based Predistortion Method for Low-Noise Amplifier Linearization

A predistortion method for CMOS low-noise amplifiers (LNAs) to be used in broadband wireless applications is presented. The method is based on the nulling of the third-order intermodulation distortion of the main amplifier by a highly nonlinear predistortion branch. Maximum nonlinearity product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and noise figure (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3-dB improvement in the third-order input intercept point with a degradation of only 1 and 0.44 dB in amplifier gain and NF, respectively. The design is based on a 0.13-mum CMOS technology     

Intermodulation distortion improvement by active compensation in an X-band IMPATT amplifier

The intermodulation products generated in an actively compensated X-band IMPATT amplifier have been measured and compared with the corresponding uncompensated amplifier. The 3rd-order intercept point increases from 11.5 dB to 23 dB, giving an improvement of 11.5 dB.     

Linearity improvement of cascode low-noise amplifiers using double DS method with a tuned inductor

We propose a highly linear low-noise amplifier (LNA) using the double derivative superposition method with a tuned inductor. This topology has an auxiliary common gate stage of the cascode amplifier to cancel each third-order intermodulation distortion (IMD3) component and can provide a high third-order input intercept point (IIP3) for the 5.25 GHz frequency band. From the simulation results using the TSMC 0.18 μm RF CMOS process, the IIP3 in the proposed cascode LNAs can be improved by 9 dB, compared with the conventional derivative superposition method. The proposed LNA achieves an IIP3 of + 15 dBm with a gain of 10.5 dB, a noise figure of 2.4 dB, and a power consumption of 6 mA at 1.5 V.     

RF transceiver and transmission line behavioral modeling in VHDL-AMS for wired RFNoC

Despite the exceptional progress of MPSoC architectures, on chip communication networks remain a lock for the evolution of their performances due to the power consumption and the delay in data carrying. In this context, the wired radio frequency (RF) network on chip (RFNoC) has emerged. In this paper, we developed a library of RF component models in VHDL-AMS for time domain simulation. This library includes mainly the transmission line (TL) and the RF transceiver components such as the low noise amplifier (LNA), the mixer and the local oscillator (LO). The models consider the conventional parameters describing their performances including the non-linearities, the noise and the bandwidth of the LNA and the mixer. Leakages between ports are also considered for the mixer. The LO model considers the traditional parameters, more importantly its phase noise. The originality of the TL model is the modeling of the skin effect on a wide frequency range for time domain simulations. All the models are validated. Global simulations are performed to demonstrate the interest to accurately model the components of the RFNoC. The developed library is used here for wired RFNoC, however it can be used for all other wired and wireless RF communication system.     

基于自适应射频预失真的多载波功率放大器线性化技术

用高功率放大器放大线性调制信号 (包络波动变化 ) ,必然会产生失真和互调成分。而基于扩频技术的第三代无线通信系统中的功率放大器必须要有很好的线性性能。本文提出一种线性化射频多载波高功率放大器的自适应射频预失真器。     

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier(LNA) with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.