超级计算机体系结构及应用情况

本文概述了当今超级计算机体系结构类型及特点，考察了国外超级计算机在气象、核模拟、CFD、生物信息学和医学、天体物理学等典型应用领域的应用情况，分析了超级计算机体系结构与应用领域之间的关系。     

基于云技术的 BIM 架构研究与实践综述

随着建筑信息模型(BIM)在建筑全生命期中得到越来越广泛的应用,建筑工程项目 的复杂性日益增长,相应的数据量也呈爆炸性增长,如何高效地支持 BIM 应用成为建筑行业面 临的重大挑战。云计算和大数据技术,尽管出现时间不长,但是已被广泛地认为能较为有效地 解决 BIM 应用面临的诸多问题,已经在学术和工业界得到了快速的接纳。为此,梳理了现有的 基于云技术的 BIM (“Cloud-BIM”)文献与实践,将现有的 Cloud-BIM 应用架构主要归纳为 3 个 层次： ､ 数据层 服务层和应用层,并针对 3 个层次上的现有研究与实践分别进行探讨和阐述, 指出不同层次上的主要研究进展和应用障碍。最后总结并展望 Cloud-BIM 架构研究与实践的热 门领域、亟待解决的问题和可能的方向,为进一步开展此研究和应用提供参考。     

Alternative Architectures and Protocols for Providing Strong Consistency in Dynamic Web Applications

Dynamic Web applications have gained a great deal of popularity. Improving the performance of these applications has recently attracted the attention of many researchers. One of the most important techniques proposed for this purpose is caching, which can be done at different locations and within different stages of the process of generating a dynamic Web page. Most of the caching schemes proposed in literature are lenient about the issue of consistency; they assume that users can tolerate receiving stale data. However, an important class of dynamic Web applications are those in which users always expect to get the freshest data available. Any caching scheme has to incur a significant overhead to be able to provide this level of consistency (i.e., strong consistency); the overhead may be so much that it neutralizes the benefits of caching. In this paper, three alternative architectures are investigated for dynamic Web applications that require strong consistency. A proxy caching scheme is designed and implemented, which performs caching at the level of database queries. This caching system is used in one of the alternative architectures. The performance experiments show that, despite the high overhead of providing strong consistency in database caching, this technique can improve the performance of dynamic Web applications, especially when there is a long network latency between clients and the (origin) server.     

基于VLIW体系结构的流相关分析*

流相关是影响VLIW(very long instruction word)结构上的循环调度的一个关键因素.目前的研究未利用VLIW的锁步特性.利用这一性质,围绕着包含这一概念,该文为VLIW结构上的流相关分析提出了一个完整的娄学模型,发现体间流相关集合可划分为若干不相交的线序集合,存在且仅存在一个独立的、全包含的流相关集合(基),使其他所有流相关都不必要.该模型允许多周期操作和条件分支.该结果可作为研究VLIW的数学基础,也可用于工程实践.     

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm

This paper presents a comprehensive overview of leakage reduction techniques prevailing in Static Random Access Memories (SRAMs) by classifying them in three categories namely latch, bitline and read port. The performance of the techniques are evaluated in terms of leakage reduction capability along with the impact on read performance and hold stability through extensive simulative investigations at 32 nm technology node by taking conventional SRAM cell as reference. Further, as SRAMs are susceptible to inter-die as well as intra-die process variations, the performance at different PVT corners is also captured to demonstrate the efficacy of each technique under PVT variations. It is found that among the techniques used for reducing latch leakages, Multi-threshold CMOS technique possess the highest leakage reduction capabilities followed by Drowsy mode and Substrate-bias techniques. The results also indicate that Negative word line technique is more effective at low supply voltages whereas the Leakage biased bitline technique is more effective at high supply voltages for reducing bitline leakages. Amongst the read port leakage reduction techniques, Stack-effect and Dynamic control of power supply rail techniques are capable of suppressing the leakages at high voltages whereas Virtual cell ground technique is more efficacious at low voltages. The impact of technology scaling on SRAM cell performance with leakage reduction techniques is also studied. For the sake of completeness, suggestions are put forward for adopting a particular technique to address leakages at latch, bitline and read port levels.     

Compiler-Optimized Simulation of Large-Scale Applications on High Performance Architectures

In this paper, we propose and evaluate practical, automatic techniques that exploit compiler analysis to facilitate simulation of very large message-passing systems. We use compiler techniques and a compiler-synthesized static task graph model to identify the subset of the computations whose values have no significant effect on the performance of the program, and to generate symbolic estimates of the execution times of these computations. For programs with regular computation and communication patterns, this information allows us to avoid executing or simulating large portions of the computational code during the simulation. It also allows us to avoid performing some of the message data transfers, while still simulating the message performance in detail. We have used these techniques to integrate the MPI-Sim parallel simulator at UCLA with the Rice dHPF compiler infrastructure. We evaluate the accuracy and benefits of these techniques for three standard message-passing benchmarks on a wide range of problem and system sizes. The optimized simulator has errors of less than 16% compared with direct program measurement in all the cases we studied, and typically much smaller errors. Furthermore, it requires factors of 5 to 2000 less memory and up to a factor of 10 less time to execute than the original simulator. These dramatic savings allow us to simulate regular message-passing programs on systems and problem sizes 10 to 100 times larger than is possible with the original simulator, or other current state-of-the-art simulators.     

扩展D-矩阵分割在测试序列生成中的应用

D-矩阵是系统装备测试与诊断的基础,为克服一般D-矩阵信息的不足,提出了一种扩展的D-矩阵,较好的反映了装备的属性,解决了D-矩阵功能故障定义中信号失效易混淆的问题;在扩展D-矩阵的测试序列生成过程中,提出了矩阵分割应用于测试序列优化的方法,用例表明该方法可显著降低计算复杂度,且提高故障隔离的指向性,避免各类测试交叉进行的情况.     

DTD与Schema在电子商务应用中的比较研究

对XMLDTD及XMLSchema在电子商务中的应用进行了比较分析。介绍了电子商务标准cXML的主要功能 ,并对cXML中主要元素的DTD定义及其PunchOut事务的工作机制进行了分析 ;对XMLSchema在电子商务中的几个重要的应用进行了详细的探讨 ,包括建立内容模式更具体且数据类型更丰富的电子商务模型 ,以及建立具有数据约束能力的电子商务模型等。     

Extended Algorithms for Approximating Variable Order Fractional Derivatives with Applications

This paper proposes accurate and robust algorithms for approximating variable order fractional derivatives of arbitrary order. The proposed schemes are based on finite difference approximations. We compare the performance of algorithms by introducing a new formulation of experimental convergence order. Two initial value problems are considered and solved by means of the proposed methods. Numerical results are provided justifying the usefulness of the proposed methods.     

Array Data Flow Analysis for Load-Store Optimizations in Fine-Grain Architectures

The performence of scientific programs on modern processors can be significantly degraded by memory references that frequently arise due to load and store operations associated with array references. We have developed techniques for optimally allocating registers to array elements whose values are repeatedly referenced over one or more loop iterations. The resulting placement of loads and stores is optimal in that number of loads and stores encoutered along each path through the loop is minimal for the given program branching structure. To place load, store, and register-to-register shift operations without introducing fully/partially redundant and dead memory operations, a detailed value flow analysis of array references is required. We present an analysis framework to efficiently solve various data flow problems required by array load-store optimizations. The framework determines the collective behavior of recurrent references spread over multiple loop iterations. We also demonstrate how our algorithms can be adapted for various fine-grain architectures.     

A Comparative Study and Evaluation of Parallel Programming Models for Shared-Memory Parallel Architectures

Nowadays, shared-memory parallel architectures have evolved and new programming frameworks have appeared that exploit these architectures: OpenMP, TBB, Cilk Plus, ArBB and OpenCL. This article focuses on the most extended of these frameworks in commercial and scientific areas. This paper shows a comparative study of these frameworks and an evaluation. The study covers several capacities, such as task deployment, scheduling techniques, or programming language abstractions. The evaluation measures three dimensions: code development complexity, performance and efficiency, measure as speedup per watt. For this evaluation, several parallel benchmarks have been implemented with each framework. These benchmarks are created to cover certain scenarios, like regular memory access or irregular computation. The conclusions show some highlights, like the fact that some frameworks (OpenMP, Cilk Plus) are better for transforming quickly a sequential code, others (TBB) have a small footprint which is ideal for small problems, and others (OpenCL) are suited for heterogeneous architectures but they require a very complex development process. The conclusions also show that the vectorization support is more critical than multitasking to achieve efficiency for those problems where this approach fits.     

Autonomic Coordination of Skeleton-Based Applications Over CPU/GPU Multi-Core Architectures

Widely adumbrated as patterns of parallel computation and communication, algorithmic skeletons introduce a viable solution for efficiently programming modern heterogeneous multi-core architectures equipped not only with traditional multi-core CPUs, but also with one or more programmable Graphics Processing Units (GPUs). By systematically applying algorithmic skeletons to address complex programming tasks, it is arguably possible to separate the coordination from the computation in a parallel program, and therefore subdivide a complex program into building blocks (modules, skids, or components) that can be independently created and then used in different systems to drive multiple functionalities. By exploiting such systematic division, it is feasible to automate coordination by addressing extra-functional and non-functional features such as application performance, portability, and resource utilisation from the component level in heterogeneous multi-core architectures. In this paper, we introduce a novel approach to exploit the inherent features of skeleton-based applications in order to automatically coordinate them over heterogeneous (CPU/GPU) multi-core architectures and improve their performance. Our systematic evaluation demonstrates up to one order of magnitude speed-up on heterogeneous multi-core architectures.     

集群政务协同业务平台架构及关键技术研究

集群政务协同平台包括六大系统。论述了该平台的应用架构和技术架构,阐述了其主要关键技术:多个政务应用的规模集成和协同应用、业务模型驱动的SOA架构通用开发平台、统一资源管理、Web服务安全增强。运行实践表明,平台能够最大限度地整合利用省(市)级政务平台的软硬件资源和政务业务资源,使农村区县基于省(市)级平台构建各自的政务平台,从而实现全省(市)政务平台的城乡统筹建设和维护,提高政务管理和协同办公的效率。     

JSP结构模型与应用分析

在介绍了JSP的基本概念及优越性的基础上,对JSP技术和ASP技术作了一个系统的比较,并详细论述了JSP的两种结构模型及相应的实例说明。最后,讨论了JSP和Java Servlet的关系以及JSP在应用方面的不足。     

Altera 28nm FPGA突破带宽瓶颈 应对云计算时代

<正>Altera继今年2月公布了28nm新工艺上的三大创新技术:嵌入式HardCopy模块、部分重新配置和28Gbps收发器技术后,于4月20日发布基于28nm的StratixV系列FPGA。"从移动互联网的演进趋势,3G网络、光纤到户、高清视频、云计算等,每年对带宽需求的增长在50%Altera公司产品及企业市场副总裁VinceHu先生     

IEEE 802.11安全架构的网络性能分析

在无线局域网中引入安全机制常造成性能下降,其中部分原因决定于对加密、认证、密钥更新和数字证书等安全选项的设置.IEEE 802.11i (WPA2)及其在新硬件平台上的实现已显著地改善了性能问题.本文对IEEE 802.11i进行性能分析,并将结论与WEP、WPA的研究进行比较.研究显示安全选项虽本质上有差异,但实践中对性能影响的差异却很小,甚至忽略不计.分析结论,为有性能要求的安全无线网络的设计提供参考.     

Internet安全体系结构的分析与比较

本文简要介绍了Internet的网络安全体系结构的现状和发展趋势,其中重点分析和比较了IPSec和SSL/TLS。文中详细阐述了IPSec和SSL/TLS的体系结构、它们所采用的安全技术、所能提供的安全服务以及它们的实现方式;并且对这两种协议的特点、应用范围、优缺点进行了介绍和比较。     

Analysis of Database System Architectures Using Benchmarks

Database machine architectures have been proposed as a promising alternative to improve database system performance, control, and flexibility. While many claims have been made for the database machine concept, few studies have been made to test the performance advantages and disadvantages of a database machine in an application environment. A comprehensive benchmark study comparing the performance of database systems on a conventional computer system and a database machine is reported in this paper. The results show the database machine architecture to have superior performance in most cases. The performance advantage is sensitive to the communication line speed between the host computer and the database machine. The effects of line speed are studied and displayed in the benchmark results. A summary of the similarities and differences between the architectures based upon our benchmark results completes the paper.