Multistage amplifier topologies with nested Gm-Ccompensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G _m feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-μm CMOS process and is tested using a ±1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58° of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm². Step response shows that the op amp is stable     

AC-Boosting Frequency Compensation with Double Pole-Zero Cancellation for Multistage Amplifiers

In this paper, we present an AC-boosting compensation topology with double pole-zero cancellation (ACBC-DPZ) for a multistage amplifier driving a very large capacitive load. The proposed technique modifies the original AC-boosting compensation (ACBC) topology to increase the power-bandwidth efficiency and reduce the size for the output power transistor and compensation capacitor. Simulation results show that the ACBC-DPZ amplifier using a CSM 0.18 μm CMOS process can achieve a unity gain bandwidth of 14 MHz and an average slew rate of 3.88 V/μs at 1500 pF load. The amplifier dissipates 2.55 mW at a 1.8 V supply.     

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6-μm process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption     

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

1.8 V–3 GHz CMOS limiting amplifier with efficient frequency compensation

A compact robust CMOS limiting amplifier (LA) for high data traffic optical links is presented in this work. The core considers two different blocks. First, four common-source inverter amplifiers are included, which optimize the gain-bandwidth product of the structure. And second, two additional compensation stages are placed strategically between the gain stages alleviating the pernicious load effect. These stages develop two different compensation techniques simultaneously thus increasing the bandwidth. The proposed design consumes 113 mW with a single 1.8 V supply. It achieves a cut-off frequency up to 3 GHz and provides a gain of 21 dB. The circuit is packaged in a QFN24 and mounted on a commercial FR4 PCB.     

Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.     

Robust feedforward compensation scheme with AC booster for high frequency low voltage buck DC–DC converters

Today and in the future, high frequency low voltage DC–DC converters are an effective power-management solution for fast transient response and small profile in portable electronic systems. This paper presents a robust feedforward compensation scheme with AC booster. An ac amplifier is added in parallel with the main path to compensate the high-frequency gain reduction, which improves gain-bandwidth (GBW) product and slew rate significantly. This approach takes the multistage error amplifier (EA) as an element in the compensation circuit instead of using passive elements used in traditional proportional-plus-integral-and-derivative (PID) compensation circuits. The positive phase shift of left-half-phase (LHP) zeros caused by the feedforward path and ac boosting path in the multistage EA is used to cancel the negative phase shift by the resonant poles of the power stage of buck DC–DC converter in order to compensate the DC–DC converters. A graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performances of the converter for the complexion arising from the presence of multiple poles of EA before crossover frequency in high frequency converters. The high gain, wide bandwidth, and high slew rate are achieved by the absence of traditional pole-splitting effect and the added ac booster. In addition, the design guidelines for this feedback compensation network realized by robust feedforward with AC booster compensation (RFACBC) scheme and multistage EA are established. When the proposed compensation networks were employed in 100 MHz buck DC–DC converter implemented in SMIC 0.18 μm CMOS process, the simulation results validate the feasibility and functionality of the RFACBC scheme and design guidelines. The closed-loop dc gain achieves over 60 dB with over 20 MHz GBW and 61° phase margin under wide range loads. Furthermore, the settling time is improved due to the advanced frequency compensation.     

Low-output-impedance class AB bipolar voltage buffer

A new ±1.5 V class AB bipolar voltage buffer that can drive low load impedance is presented. A current compensation technique is used for achieving a low output impedance, resulting in a large unitary gain bandwidth and low distortion. Simulation results are included demonstrating the circuit performance     

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A fully balanced CMOS Variable Gain Amplifier (VGA) based on current-mode techniques suitable for high frequency applications and large signals is presented. The VGA consists of an analog multiplier, current gain stages, and resistive loads. A frequency compensation scheme based on a capacitive feed-forward technique increases the bandwidth by more than 60%. Common-Mode Feed-Forward (CMFF) techniques are used to minimize dc offsets. The gain can be programmed from 0 to 42 dB with ?3 dB bandwidth greater than 270 MHz; a gain calibration scheme for precise gain control applications is included. The Third Harmonic Distortion (HD3) is less than ?55 dB for differential input and output voltages of 1 V_pk-pk. The VGA was fabricated in a standard 0.35 μm CMOS process, and consumes around 54 mW from a single power supply of 2.7 V.     

用于低功耗三级放大器的嵌套式密勒有源电容频率补偿技术

提出了一种新的用于低功耗,节省面积的三级放大器频率补偿技术.该技术将有源电容进行嵌套连接从而克服了传统的嵌套式密勒补偿与反嵌套式密勒补偿的缺点.当将这一技术用标准的0.35μm工艺设计成电路并负载150pF电容时,放大器实现了105dB直流增益,3.3M的增益带宽积,68°相位裕度以及2.56V/μs的平均转换速率.而这一切的实现是在2V电源电压仅消耗40μW的功耗以及使用了很小的补偿电容.     

High-gain,high-bandwidth,rail-to-rail,constant-gm CMOS operational amplifier

This study presents a high-gain, high-bandwidth, constant-g_m , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18?µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181?×?173?µm² and it consumes a power of 2.41?mW at a supply voltage of 1.8?V. The op-amp achieves a dc gain of 94.3?dB and a bandwidth of 45?MHz when the output capacitive load is connected to an effective load of 42.5?pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6?mA and an SR of 17?V/µs.     

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

A new technique for designing uniform multistage amplifiers (MAs) for high-frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. The intrinsic capacitances within transistors are exploited by the active negative feedbacks to expand the bandwidth. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Using the proposed topology, a six-stage amplifier in TSMC 0.35-mum CMOS process was designed. Measurement results show that the gain can be varied between 16 and 44 dB within 0.7-3.2-GHz bandwidth with less than 5.2-nV /radicHz noise. Die area of the amplifier is 175 mum times 300 mum.     

一种低功耗高分辨率可编程增益放大器的设计

该文设计了一种用于零中频接收机的低功耗高分辨率可编程增益放大器。该放大器采用源级电阻负反馈结构,利用跨导增强技术提高了放大器的线性度,并加入补偿电容扩展了带宽,实现了低功耗设计。该可编程增益放大器采用0.25μmCMOS工艺,仿真结果表明,在0.5pF负载电容的情况下,放大器增益动态的范围是0～62dB,2.5V供电电压下最大功耗为2.2mW,增益分辨率达到0.25dB,带宽10MHz,0dB增益时输入三阶交调点为17.9dBm。     

Low-voltage low-power opamp based amplifiers

Amplifiers operating under low-voltage and low-power conditions are strongly limited in dynamic range and bandwidth. The maximum dynamic range is limited by the supply power and the thermal noise power in resistors. To obtain the maximum, input and output stages should be able to process signals from rail to rail. Several rail-to-rail input stages and rail-to-rail output stages biased in current-efficient class-AB mode are presented. Also, the bandwidth is limited by the low-power constraint. To reach the maximum bandwidth at sufficient DC gain, the effectivity of several frequency compensation structures is compared, such as Parallel, Miller, and Nested Miller Compensation. Finally, it is shown that the Multipath Nested Miller Compensation combines a very high bandwidth with high gain, while being insensitive to process parameters.     

Improving GBW product on CMOS operational transconductance amplifiers by interleaved feedforward paths

This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.     

A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.     

A 1-GHz bipolar class-AB operational amplifier with multipathnested Miller compensation for 76-dB gain

A 1-GHz operational amplifier with a gain of 76 dB while driving a 50-Ω load is presented. The equivalent input noise voltage is as low as 1.2 nV/√Hz. This combination of extremely high bandwidth, high gain, and low noise is the result of a three-stage all-n-p-n topology combined with a multipath nested Miller compensation. Using 10-GHz f_T n-p-n transistors, the realizable bandwidth could be of the order of 2-3 GHz. However, bond-wire inductances restrict the useful bandwidth to 1 GHz. The amplifier occupies an active area of 0.26 mm² and has been realized in the bipolar part of a 1-μm BiCMOS process     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

一种具有温度补偿的宽带CMOS可变增益放大器

设计实现了一个具有温度补偿的宽带CMOS可变增益放大器,该可变增益放大器的核心电路由三级基于改进型Cherry-Hooper结构的可变增益单元级联而成,并通过一种温度系数增强的且可编程的偏置电路和增益控制电路对可变增益放大器的增益进行温度补偿。采用中芯国际0.13μm CMOS工艺流片,测试结果表明可变增益放大器的可变增益范围为-13～27dB,经过温度补偿后,在相同增益控制电压下其增益在0～75°C温度范围内的变化范围不超过3dB。可变增益放大器的3dB带宽为0.8～3GHz,输入1dB压缩点为-50～-21dBm,在1.2V电压下,功耗为21.6mW。