Novel stray-insensitive SC bandpass filter

A new stray-insensitive SC bandpass filter derived from Moschytz's modified Tarmy-Ghausi configuration is described. Design equations and comparison with the Fleischer-Laker biquad are presented.     

Inductorless CMOS RF bandpass filter

The design and experimental results of a novel CMOS RF filter are presented. Employing a pair of current-reused active inductors, a differential second-order bandpass filter working at 900 MHz with Q=41 has been implemented in a 0.35 μm CMOS process     

A 500-nA sixth-order bandpass SC filter

A sixth-order bandpass switched-capacitor (SC) filter that requires only 500 nA of total supply current has been designed and fabricated in a 2-μm CMOS technology. The filter is part of an implantable device powered by a ±1.2-V battery; it can drive up to 30 pF of capacitive load and uses a 2-kHz sampling frequency. A substantial reduction in the power consumption has been achieved by using a novel amplifier time-sharing technique that allows the realization of an arbitrary number of biquadratic cells with only two amplifiers. Further power saving was obtained with the use of positive feedback in the amplifier input stage to enhance its transconductance. The prototype chip requires an area of 2200 mils²     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

Low-voltage low-power high-Q CMOS RF bandpass filter

Based on the gyrator-C inductor topology, a second-order bandpass filter can be realised by adding a series capacitor to the input port of the gyrator. high-Q second-, fourth- and sixth-order fully differential RF bandpass filters operating in the 2.4 GHz Industrial, Scientific and Medical (ISM) frequency band under a 2 V single power supply voltage with low-power dissipation are demonstrated     

A high-Q bandpass fully differential SC filter with enhancedtestability

This paper presents a low-cost testing approach for switched-capacitor filters. A design for testability (DfT) methodology is discussed, and a system-level architecture is proposed providing capabilities for an off- and on-line test as well as a built-in self-test (BIST). To prove the feasibility of this approach, it has been applied to a sixth-order high-Q bandpass switched-capacitor (SC) filter. The benefit is a significant testability enhancement without degrading filter behavior. Experimental results from a silicon prototype are also presented     

A CMOS bandpass filter for low-IF bluetooth receivers

A CMOS fully integrated 12th-order bandpass filter for low interemdiate frequency Bluetooth receivers is presented. The design is optimized to meet the selectivity and dynamic range requirements of Bluetooth while consuming relatively low power. The filter is based on unity gain cells and utilizes linearized MOSFET resistors for tuning. It exhibits a bandwidth of 1 MHz and a programmable center frequency range of 2 to 4 MHz. Experimental results obtained from a standard 0.5-/spl mu/m CMOS chip show that the filter exhibits an in-band dynamic range of 53.3 dB at gain of 0 dB, and 52 dB at gain of 15 dB, while consuming a total current of 1.32 mA. Attenuations of more than 10, 38, and 55 dB, are achieved for blockers one, two, and three, respectively.     

A 200 MHz CMOS Q-enhanced LC bandpass filter

This paper presents design techniques and performance bounds for implementing Q-enhanced, LC bandpass filters in silicon IC technologies. These filters offer significant advantages over switched capacitor and Gm-C based designs, including higher frequency of operation and lower power consumption for a given dynamic range. A prototype 200 MHz, fourth-order filter implemented in a 2 μm n-well CMOS process is described, and measured performance is compared with theoretical predictions. The prototype filter operates at a selectivity Q of 100 and draws less than 8 mA when operating from 3 to 5 V supplies, making it potentially suitable for use as a first IF filter in modern cellular and PCS receivers     

An OTA-based CMOS bandpass filter for NMR applications

One of the very popular medical imaging techniques used in present-day radiology is the magnetic resonance imaging (MRI) which is based on the phenomenon of nuclear magnetic resonance (NMR) in the hydrogen atoms present in the body. There is ever-increasing research in electronic circuit design for biomedical applications using NMR. Earlier magnetic resonance imagers operated at a magnetic field strength of 0.3?T. The present imagers operate at a magnetic field of 1.5?T, the resonance frequency of the nuclei being 64?MHz. This article presents a CMOS bandpass filter (BPF) design for NMR applications. The overall BPF design is realised in 180?nm CMOS technology which occupies an active area of 24.23?×?33.125?µm² and consumes 0.165?mW of power from a 1.5?V supply.     

Design of fractal-based CMOS bandpass filter for WirelessHD system

We proposed a fractal-based dual-mode bandpass filter (BPF) using a standard CMOS process for application of 60 GHz WirelessHD system. We first investigated the effect of coupling feedlines of I/O ports set at different layer of M3 and M4 layer on the transmission loss of the resonator, and verified the nature coupling of fractal-based dual-mode filter. Experimental result shows that the designed filter with a fractional-bandwidth (FBW) of 23%, an insertion loss about 7 dB and return loss larger than 10 dB. Additionally, two transmission zeros are appeared at the passband edges, thus much improve the selectivity of the proposed CMOS BPF. The result indicates that fractal-based structure is feasible and can meet the requirement in the mm-wave application.     

A 48-16-MHz CMOS SC decimation filter

This paper presents a CMOS switched-capacitor decimation filter for prefiltering operations in video communications systems, reducing the complexity of continuous-time antialiasing filters and alleviating dynamic range requirements of analog-to-digital converters. As a consequence of the structure's low sensitivity to process variations, predicted by theory and verified in the laboratory by measurements on all samples of the same batch, it was possible to apply capacitor arrays having minimum feasible size units of 100 fF to implement the filter coefficients, leading to substantial savings in power consumption. Implemented in a standard 0.8-/spl mu/m CMOS process with poly-poly capacitors, the experimental device samples the incoming continuous-time analog signal at 48 MHz and presents a filtered sampled-data output at 16 MHz, with a measured pass-band deviation smaller than 0.22 dB up to the cutoff frequency of 3.6 MHz, output noise power spectrum of 1.1 nV/sub RMS///spl radic/(Hz) and a signal handling ability of 1.4 V/sub pp/, resulting in a dynamic range of 48 dB, meeting the usual specifications for video-frequency signal processing.     

Integrated CMOS SC filter with 170 kHz cutoff frequency

Based on the theory of switched capacitor (SC) filters using voltage invertor switches (VIS) a third order lowpass filter has been designed and integrated in a standard CMOS metal gate technology. The filter uses a bottom plate stray-insensitive VIS and requires only unity gain buffers. Performance parameters of an integrated version are: cutoff frequency 170 kHz, dynamic range 70 dB, and power dissipation 12 mW.     

Micromachined V-band CMOS bandpass filter with 2 dB insertion loss

A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (vz1) and the high-frequency transmission-zero (vz2) can be tuned by the series-feedback capacitor Cs and the parallelfeedback capacitor Cp, respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion loss (1/S21) lower than 3 dB over the frequency range 52.5?76.8 GHz. The minimum insertion loss was 2 dB at 63.5 GHz, the best results reported for a V-band CMOS bandpass filter in the literature.     

CMOS RF switched capacitor bandpass filter tuned by ring VCO

A new RF switched capacitor bandpass filter and its command circuit made up of a ring voltage controlled oscillator with ‘XOR’ gates are proposed. Implemented in a standard CMOS technology, this circuit is intended to be used in a subset of professional mobile phone applications [380–520 MHz]. Experiments carried out on a prototype show a tunable center frequency range of 260 MHz [240–500 MHz], with a quality factor that can be as high as 300.     

60 GHz compact integrated cross-coupled SIR-MH bandpass filter on bulk CMOS

A new 60 GHz fourth-order cross-coupled bandpass filter using a step- impedance-resonator (SIR) miniaturised open-loop resonator and the miniaturised-hairpin (MH) resonator was designed and fabricated on 0.13 mum bulk CMOS. It has 8.5 GHz (58-66.5 GHz) bandwidth, 5.9 dB insertion loss, and better than 10 dB return loss over the whole passband, and exhibits high selectivity and a compact size of 714.9 times 484 mum (0.346 mm ). This filter is the first reported cross-coupled filter above 40 GHz on CMOS.     

A 3 V 10 MHz pseudo-differential SC bandpass filter using gainenhancement replica amplifier

This paper describes the design strategy and implementation of a high frequency low voltage pseudo-differential SC filter which use opamps with gain enhancement replica amplifier. Experimental results of a biquad SC bandpass with a center frequency of 10 MHz and a Q of 10 are presented. The realized opamp has an open-loop unity-gain bandwidth of 850 MHz, a phase margin of about 62°, and a dc gain of 50 dB. The prototype filter dissipates 23 mW from a 3 V supply and occupies 0.3 mm ² in a 0.8 μm N-well single-poly, double-metal CMOS process     

A highly linear CMOS Gm-C bandpass filter with on-chipfrequency tuning

A fourteenth-order CMOS transconductance-C (G_m-C) bandpass filter with on-chip automatic frequency tuning is described. By using highly linear G_m-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured intermodulation distortion (IM3) @ 600 kHz for a 4 V_pp input signal is only -61 dB. On-chip automatic frequency tuning provides more than 300% center frequency range (i.e., 165-505 kHz) of the filter with ±1% frequency accuracy. The 0.7-μm CMOS filter measures 4.8 mm ² and consumes 70 mW from a single 5 V power supply     

An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz.     

A 10.7-MHz CMOS SC radio IF filter using orthogonal hardwaremodulation

FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm² in a 0.6 μm CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filters     

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-railoutput swing

A low-voltage switched capacitor (SC) filter operated from a single 1 V supply and realized in a standard 0.5-μm CMOS technology is presented. Proper operation is obtained using the switched-opamp technique without any clock voltage multiplier or low-threshold devices. This makes the circuit compatible with future deep submicrometer technology. As opposed to previous switched-opamp implementations, the filter uses a fully differential topology. This allows operation with a rail-rail output swing and reduction of the number of opamps required to build high order infinite impulse response (IIR) filters. On the other hand, a low-voltage common-mode feedback (CMFB) circuit is required. In addition, the circuit uses an opamp which is only partially turned off during the off phase. This enables an increase in the maximum sampling frequency. The filter implements a bandpass response (f_s/f _o=4, Q=7) and it has been characterized with a 1.8 MHz sampling frequency. Its power consumption is about 160 μW. The filter is still fully functional down to 0.9 V supply voltage