Electroluminescence from the Ge quantum dot MOS tunneling diodes

A Ge quantum dot (QD) light-emitting diode (LED) is demonstrated using a MOS tunneling structure for the first time. The oxide film was grown by liquid phase deposition at 50/spl deg/C to reduce the thermal budget. The infrared emission of /spl sim/1.5 /spl mu/m was observed from Ge QD MOS LEDs, similar to the p-type-intrinsic-n-type structure reported previously. At the negative gate bias, the electrons in the Al gate electrode tunnel to the Ge QD through the ultrathin oxide and recombine radiatively with holes to emit the /spl sim/1.5/spl mu/m infrared. The electrons also recombine with holes in the Si cap, and the band edge emission from Si is also observed.     

Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling

Low-frequency flicker noise in analog n-MOSFETs with 15-/spl Aring/ gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

Slow transients in polyimide-passivated InP-InGaAs HBTs: effects of UV irradiation, thermal annealing and electrical stress

The effects of UV irradiation, thermal annealing and electrical bias on the base current instability in polyimide (PI)-passivated InP-based heterojunction bipolar transistors (HBTs) have been studied. The base current transient could be effectively suppressed by UV irradiation. The suppression of current transient by UV irradiation can be attributed to the reduction of the near interface trap density in the PI, which has long-term stability at room temperature. However, baking the device at a temperature higher than 100 /spl deg/C may induce a significant increase in PI trap density as well as the broadening of spatial electron trap distribution causing the enhancement of current transient, and the current transient induced by electrical stress could be directly related to the device self-heating through thermal annealing effect.     

Gate-first Germanium nMOSFET with CVD HfO/sub 2/ gate dielectric and silicon surface passivation

A gate-first self-aligned Ge n-channel MOSFET (nMOSFET) with chemical vapor deposited (CVD) high-/spl kappa/ gate dielectric HfO/sub 2/ was demonstrated. By tuning the thickness of the ultrathin silicon-passivation layer on top of the germanium, it is found that increasing the silicon thickness helps to reduce the hysteresis, fixed charge in the gate dielectric, and interface trap density at the oxide/semiconductor interface. About 61% improvement in peak electron mobility of the Ge nMOSFET with a thick silicon-passivation layer over the CVD HfO/sub 2//Si system was achieved.     

Si-H bond breaking induced retention degradation during packaging process of 256 mbit DRAMs with negative wordline bias

Data retention degradation of a 256-Mbit DRAM during the packaging process is investigated in this paper. Electrical measurement and device simulation show that a trap-assisted leakage degrades the retention time even in packaging process at about 250/spl deg/C. Retention time of the degraded chip is strongly dependent on the negative wordline voltage and operation temperature, but less sensitive to the substrate bias. Trap-assisted gate induced drain leakage is proposed as the mechanism of retention loss in the degraded chip. The degraded chips usually can be repaired by another thermal baking process. We propose Si-H bond breaking and the subsequent trap generation at the gate and drain overlap region as the root cause of retention degradation according to the fact that the Si-H bond density of backend passivation oxide and nitride layers correlate well with the retention performance of DRAM chips with negative wordline bias. Moreover, the packaged chip shows variable retention behavior during a thermal baking of 250/spl deg/C. Theoretical calculation indicates that the trap generation or movement to the high electrical field region beneath the gate can increase the trap-assisted gate induced drain leakage by about an order of magnitude.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

The thermal stability of one-transistor ferroelectric memory with Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-poly-SiO/sub 2/-Si gate stack

The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-Poly-SiO/sub 2/-Si was characterized in the temperature range of -10/spl deg/C to 150/spl deg/C. The memory windows decrease when the temperatures are higher than 60/spl deg/C. The drain currents (I/sub D/) after programming to on state decrease with increasing temperature. The drain currents (I/sub D/) after programming to off state increase with increasing temperature. The ratio of drain current (I/sub D/) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150/spl deg/C. On the other hand, the memory window and the ratio of I/sub D/(on)/I/sub D/(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10/spl deg/C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60/spl deg/C.     

Threading Dislocation Induced Low Frequency Noise in Strained-Si nMOSFETs

The correlations between the threading dislocations and the low-frequency noise characteristics of the n-type strained-Si field-effect transistors are studied using the devices with different sizes. The device-area-dependent$S_ VG$(power spectral density of the gate referred voltage noise) ratio of the strained-Si devices over the control Si devices obtained form geometric average can be understood by the modified carrier number fluctuation model with excess traps from the Poisson distributed threading dislocations. The equivalent trap number per threading dislocation extracted from the area-dependent$S_ VG$ratios is$sim$85 for the strained-Si devices, and which results in$sim$4.2X degradation of the$S_ VG$for the strained-Si device with the device area of 625$muhbox m^2$.     

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.     

Power transistors fabricated using isotopically purified silicon (/sup 28/Si)

It is well known that isotopic purification of group IV elements can lead to substantial increases in thermal conductivity due to reduced scattering of the phonons. The magnitude of the increase in thermal conductivity depends on the level of isotopic purification, the chemical purity, as well as the test temperature. For isotopically pure silicon (/sup 28/Si) thermal conductivity improvements as high as sixfold at 20 K and 10%-60% at room temperature have been reported. Device heating during operation results in degradation of performance and reliability (electromigration, gate oxide wearout, thermal runaway). In this letter, we discuss the thermal performance of packaged RF LDMOS power transistors fabricated using /sup 28/Si. A novel technique allows the cost effective deployment of this material in integrated circuit manufacturing. A clear reduction of about 5/spl deg/C-7/spl deg/C in transistor average temperature and a corresponding 5%-10% decrease in overall packaged device thermal resistance is consistently measured by infrared microscopy in devices fabricated using /sup 28/Si over natural silicon.     

Reducing dark current in a high-speed Si-based interdigitated trench-electrode MSM photodetector

The authors have studied higher dark-current temperature dependence in a trench-electrode Si-based metal-semiconductor-metal (MSM) photodetector which has a hydrogenated intrinsic amorphous silicon (i-a-Si:H) dark-current suppression layer. The poor dark-current temperature-dependence performance could be improved significantly by reducing the number of trap states in the depletion region of the reverse-biased crystalline/amorphous Si heterojunction. To reduce the trap states, a modified plasma-enhanced chemical vapor deposition (PECVD) system, which reduced the ion bombardment on the Si substrate, was employed to deposit an i-a-Si:H layer. Moreover, since fewer trap states in a photodetector will result in a degradation of the fall time of the temporal response of the device, a Ti electrode, which has a lower Schottky barrier height (0.62 eV) than that (0.84 eV) of the previous Cr electrode used with i-a-Si:H, was employed for compensation. The device obtained exhibited very good dark-current stability and temporal response. The dark current only increased from 6 to 34 nA, when the operating temperature was increased from room temperature (R. T.) to 57/spl deg/C, much lower than that of the previously reported 3-V bias voltage one (from 22 to 209 nA). Device responsivity and quantum efficiency also showed obvious improvement, both at R. T. (0.192 A/W and 0.29) and 57/spl deg/C (0.213 A/W and 0.32, respectively) and were higher than those previously reported (0.174 A/W and 0.26, at 57/spl deg/C).     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Thermally stable Ge/Ag/Ni Ohmic contact for InAlAs/InGaAs/InP HEMTs

Excellent annealed ohmic contacts based on Ge/Ag/Ni metallization have been realized in a temperature range between 385 and 500/spl deg/C, with a minimum contact resistance of 0.06 /spl Omega//spl middot/mm and a specific contact resistivity of 2.62 /spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ obtained at an annealing temperature of 425/spl deg/C for 60 s in a rapid thermal annealing (RTA) system. Thermal storage tests at temperatures of 215 and 250/spl deg/C in a nitrogen ambient showed that the Ge/Ag/Ni based ohmic contacts with an overlay of Ti/Pt/Au had far superior thermal stabilities than the conventional annealed AuGe/Ni ohmic contacts for InAlAs/InGaAs high electron mobility transistors (HEMTs). During the storage test at 215/spl deg/C, the ohmic contacts showed no degradation after 200 h. At 250/spl deg/C, the contact resistance value of the Ge/Ag/Ni ohmic contact increased only to a value of 0.1 /spl Omega//spl middot/mm over a 250-h period. Depletion-mode HEMTs (D-HEMTs) with a gate length of 0.2 /spl mu/m fabricated using Ge/Ag/Ni ohmic contacts with an overlay of Ti/Pt/Au demonstrated excellent dc and RF characteristics.     

A high efficient 820 nm MOS Ge quantum dot photodetector

A Ge quantum dot photodetector has been demonstrated using a metal-oxide-semiconductor (MOS) tunneling structure. The oxide film was grown by liquid phase deposition (LPD) at 50/spl deg/C. The photodetector with five-period Ge quantum dot has responsivity of 130, 0.16, and 0.08 mA/W at wavelengths of 820 nm, 1300 nm, and 1550 nm, respectively. The device with 20-period Ge quantum dot shows responsivity of 600 mA/W at the wavelength of 850 nm. The room temperature dark current density is as low as 0.06 mA/cm/sup 2/. The high performance of the photodetectors at 820 nm makes it feasible to integrate electrooptical devices into Si chips for short-range optical communication.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

High work function Ir/sub x/Si gates on HfAlON p-MOSFETs

We have fabricated the fully silicided Ir/sub x/Si-gated p-MOSFETs on HfAlON gate dielectric with 1.7-nm equivalent oxide thickness. After 950/spl deg/C rapid thermal annealing, the fully Ir/sub x/Si/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm/sup 2//V/spl middot/s, and the advantage of being process compatible to the current VLSI fabrication line.