新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

热载流子诱生MOSFET/SOI界面陷阱的正向栅控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究 .正向栅控二极管技术简单、准确 ,可以直接测得热载流子诱生的平均界面陷阱密度 ,从而表征器件的抗热载流子特性 .实验结果表明 :通过体接触方式测得的MOSFET/SOI栅控二极管R G电流峰可以直接给出诱生的界面陷阱密度 .抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系 ,指数因子约为 0 787     

热载流子诱生MOSFET／SOI界面陷阱的正向机控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究。正向栅控二极管技术简单、准确，可以直接测得热载流子诱生的平均界面陷阱密度，从而表征器件的抗热载流子特性。实验结果表明：通过体接触方式测得的MOSFET/SOI栅控二级管R-G电流峰可以直接给出诱生的界面陷阱密度。抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系，指数因子约为0.787。     

正向栅控二极管监测F-N电应力诱生的SOI-MOSFET界面陷阱

报道了正向栅控二极管R-G电流法表征F-N电应力诱生的SOI-MOSFET界面陷阱的实验及其结果．通过体接触的方式实现了实验要求的SOI-MOSFET栅控二极管结构．对于逐渐上升的累积应力时间,测量的栅控二极管电流显示出明显增加的R-G电流峰值．根据SRH理论的相关公式,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加,指数为0.4.这一实验结果与文献先前报道的基本一致．     

正向栅控二极管监测F- N电应力诱生的SOI- MOSFET界面陷阱

报道了正向栅控二极管 R- G电流法表征 F- N电应力诱生的 SOI- MOSFET界面陷阱的实验及其结果 .通过体接触的方式实现了实验要求的 SOI- MOSFET栅控二极管结构 .对于逐渐上升的累积应力时间 ,测量的栅控二极管电流显示出明显增加的 R- G电流峰值 .根据 SRH理论的相关公式 ,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加 ,指数为 0 .4.这一实验结果与文献先前报道的基本一致     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

线性余因子差分亚阈电压峰技术测量电应力诱生MOSFET界面陷阱的研究

本文提出了用线性余因子差分亚阈电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证 .详细介绍了该方法的基本原理和实验实现 ,得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系 .该方法具有普适性 ,可用于MOSFET的一般可靠性研究和寿命预测 .     

线性余因子差分亚阀电压峰技术测量电应力诱生MOSFET界面陷阱的研究

本文提出了用线性余因子差分亚阀电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证，详细介绍了该方法的基本原理和实验实现，得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系，该方法具有普适性，可用于MOSEFT的一般可靠性研究和寿命预测。     

正向栅控二极管的R-G电流直接表征NMOSFET

使用半导体器件数值分析工具DESSISE-ISE,对正向栅控二极管R-G电流表征NMOSFET沟道pocket或halo注入区进行了详尽的研究.数值分析表明:由于栅控正向二极管界面态R-G电流的特征,沟道工程pocket或halo注入区的界面态会产生一个独立于本征沟道界面态R-G电流特征峰的附加特征峰.该峰的幅度对应于pocket或halo区的界面态大小,而其峰位置对应于pocket或halo区的有效表面浓度.数值分析还进一步显示了该附加特征峰的幅度对pocket或halo 区的界面态变化的敏感性和该峰的位置对pocket或halo区的有效表面浓度变化的敏感性.根据提出的简单表达式,可以用实验得到的R-G电流的特征直接抽取沟道工程的pocket或halo注入区的界面态和有效表面浓度.     

MOS器件栅介质层陷阱的表征方法

随着MOS器件按比例缩小,MOS器件的可靠性问题正成为限制器件性能的一大瓶颈。作为可靠性研究的一个热点和难点,MOS器件栅介质可靠性的研究一直是学术界和工业界研究的重点。普遍认为,栅介质中的陷阱是引起栅介质退化乃至击穿的主要因素,对栅介质中陷阱信息的准确提取和分析将有助于器件性能的优化、器件寿命的预测等。针对几十年来研究人员提出的各种陷阱表征方法,在简单介绍栅介质中陷阱相关知识的基础上,对已有的界面陷阱和氧化层陷阱表征方法进行系统的调查总结和分析,详细阐述了表征技术的新进展。     

DC pulse hot-carrier-stress effects on gate-induced drain leakagecurrent in n-channel MOSFETs

The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation     

Generation-recombination noise in the near fully depleted SIMOX SOI n-MOSFET - physical characteristics and modeling

Noise measurement in the linear regime of the device characteristics shows the evolution of an important Lorentzian-like component in the thin-film SIMOX silicon-on-insulator (SOI) n-MOSFET, during the transition from fully depleted to near fully (or partially) depleted operation. The same noise component co-exists with another Lorentzian-like component commonly observed in the kink region, thus distinguishing it from the latter, which is associated with a shot-noise mechanism. Evidence unambiguously shows that local potential fluctuations, caused by random generation-recombination (G-R) processes at bulk defects in the depleted SOI film, are primarily responsible. Extracted trap energy of /spl sim/0.4-0.45 eV below the silicon conduction band edge confirms the involvement of deep-level electron traps, which are probably linked to the residual oxygen and SiO/sub 2/ precipitates in the SOI film. A new analytical G-R noise model yields bulk traps with an average density of /spl sim/10/sup 16/ cm/sup -3/, situated at /spl sim/22-32 nm from the front interface. With an area density comparable to that of the front interface states, the proximity of these bulk traps to the conducting channel in thin-film SIMOX SOI devices accounts for the dominance of bulk-trap induced G-R noise over conventional 1/f noise due to near-interface oxide traps.     

Back and front interface related generation-recombination noise inburied-channel SOI pMOSFETs

This paper reports on a detailed study of generation-recombination (GR) noise in buried-channel silicon-on-insulator (SOI) pMOSFETs, occurring in the linear operation mode. In particular, the plateau amplitude and the corner frequency (relaxation time τ) of the Lorentzian are investigated as a function of the front (V_Gf) and of the back gate bias (V_Gb). It is shown that different cases can be distinguished, depending of the conduction mode of the device, i.e. for surface or buried channel operation. For surface channel operation the GR noise parameters are strongly influenced by the back gate bias and only weakly dependent on V_Gf. The opposite is true when the front interface starts to deplete, thereby pushing the channel deeper into the Si film. As is shown, the relaxation time depends exponentially on either V_Gf or V_Gb. A similar exponential gate-bias dependence is found for the Lorentzian amplitude. Based on the observations, it is concluded that the GR noise originates from the front or the back interface, depending on the operation mode. The effective density of front and back interface traps can be derived from the GR noise amplitude     

MOS器件辐照引入的界面态陷阱性质

通过分析总剂量辐照产生的界面陷阱的施主和受主性质 ,用半导体器件模拟软件 Medici模拟了NMOS、PMOS器件加电下辐照后的特性。结果表明 ,对于 NMOSFET,费米能级临近导带 (N沟晶体管反型 )时 ,受主型界面态为负电荷 ,施主型界面态陷阱为中性 ,使界面态陷阱将引起的阈值电压漂移 ;而对 PMOSFET,当费米能级临近价带 (P沟晶体管反型 )时 ,施主型界面态陷阱带正电荷 ,受主型界面态陷阱为中性 ,界面态陷阱将引起负的阈值电压漂移。理论模拟的转移特性与测试结果吻合。文中从器件工艺参数出发 ,初步建立了总剂量电离辐照模型 ,该模型对于评估器件总剂量加固水平提供了一种理论方法     

界面陷阱对InSb光伏型红外探测器稳态特性的影响

基于Silvaco二维数值仿真研究了界面陷阱对背照式p-on-n台面型In Sb光伏红外探测器串音和量子效率的影响,通过分析探测器中复合率分布、空穴电流密度分布、电场分布等与界面陷阱的空间分布及浓度的相关性,揭示了界面陷阱影响探测器的稳态性能的内在物理机制.研究结果表明,N-型In Sb有源区与钝化层界面处的陷阱和像元台面间的界面陷阱都会在提高串音性能的同时降低量子效率,但由于两者作用区域不同,所以对两种性能的影响程度不同.     

Low-frequency noise in depletion-mode SIMOX MOS transistors

Low-frequency noise measurements in depletion-mode SIMOX MOSFETs are reported. A simple model provides a reliable interpretation of the low-frequency noise in multi-interface depletion-mode transistors. An experimental procedure to separate noise contributions of front and back interfaces from noise due to bulk carrier fluctuations is described. The noises generated in the thin Si film and at the two Si-SiO₂ interfaces can be identified and characterized independently in terms of bulk properties and interface trap densities. Single-level traps at the back interface and defects in the volume are detected in high-temperature annealed materials     

Random telegraph signals in accumulation-mode SOI/nMOSFETs

Random telegraph signals (RTS's) arising from interfacial defects in small accumulation-mode SOI/nMOSFETs have been studied. By analyzing the average capture time of each RTS as a function of both the front-gate and back-gate voltages, the authors are able to distinguish between defects at the front interface from those at the back interface. In contrast to the RTS's typically observed in enhancement-mode MOSFETs where only those interfacial defects within an energy range close to the Si band edge can be measured, the use of the accumulation-mode SOI/nMOSFET makes it possible to probe interface traps near midgap     

A front-gate charge-pumping method for probing both interfaces inSOI devices

A simple front-gate charge pumping technique has been developed, which enables the measurement of interface traps at both the front and the back interfaces of a fully depleted (FD) SOI/MOSFET. It is based on the strong coupling between the two interfaces, and its validity has been verified both experimentally and by computer simulation. Experiments have been performed on both SOI/MOSFET's and SOI/PMOSFET's. This front-gate charge pumping technique is then utilized to study the hot-carrier induced degradation in SOI/NMOSFET's. It has been found that the back channel is physically damaged after front-channel hot-carrier injection. Front-gate Fowler-Nordheim (FN) injection has been found to cause damage at the front interface only