并行数字匹配滤波器的设计

介绍了匹配滤波器原理,分析了匹配滤波并行处理的算法,提出了一种适合高速处理的并行数字匹配滤波器的设计方法。使用Matlab软件进行了仿真,根据仿真结果证明了此设计方法可行。给出了利用可编程门阵列(Field-Programmable Gate Array,FPGA)实现16阶高速并行数字匹配滤波器的方案,指出了实现的要点。在系统中进行了性能测试,结果表明,采用该并行处理算法实现的数字匹配滤波器适合高速信号处理。     

Implementation of a tracking Kalman filter on a digital signalprocessor

A Kalman filter for tracking moving objects has been implemented on a TMS32010 digital signal processor. Tracking accuracy and quantization effects of the implementation have been measured by comparing the filter to one implemented on a general-purpose computer with a 32 bit word length. The filter design has been optimized to minimize the program memory requirements and execution speed. Although the filter has been implemented on a specific signal processing chip, the design is general enough to be applicable to any other digital signal processor. The filter can be used for tracking objects for industrial or other applications where range and bearing measurements are available. For motion on a plane, the filter can be used to track objects where the maximum system bandwidth is 1680 Hz; for three-dimensional motion the system bandwidth is 1120 Hz. Using the approach presented, higher system bandwidth can be accommodated through higher-speed digital signal processors     

基于TMS320VC5509DSP的FIR数字滤波器的实现

FIR数字滤波器广泛应用于实时数字信号处理领域.本文介绍了FIR数字滤波器的结构、特点及设计方法,并采用窗函数法设汁了FIR滤波器.利用TMS320VC5509 DSP芯片强大的数字信号处理功能实现了该滤波器.实验表明,此数字滤波器工作稳定,能够满足实时的滤波处理功能.     

基于FPGA的高速数字FIR滤波器设计

本文在分析传统FIR数字滤波器的基础上,设计了一种面向时序和面积优化的高速数字FIR滤波器结构。和传统的数字FIR滤波器比较,该结构具有速度快,面积小,易于扩展等特点。采用该结构,实现了一个基于FPGA的14阶的数字FIR滤波器。     

数模混合电路实现一维模拟小波变换芯片

整个电路采用标准CMOS工艺,采取模块化设计的方法,把数字频率发生器和模拟滤波器部分分开设计。数字频率发生器采用直接数字综合(DDS)的方式,来产生5种不同中心频率(10个通道),简化了传统模拟压控振荡器(VCO)的设计,提高了频率发生器的灵活性;根据精度要求,模拟高斯低通滤波器采用5阶低通滤波器来进行逼近。并论述和讨论了一种用数字和模拟混合集成电路来实现一维模拟输入的连续小波变换(CWT)芯片的方法。     

一种改进的适用于Sigma-Delta ADC的数字抽取滤波器

数字滤波器在sigma-delta ADC芯片中占据了大部分芯片面积,该文提出了一种数字滤波器结构,这种结构滤波器采用一个控制单元和一个加法器取代了Hogenauer结构滤波器中差分器的多个加法器,从而减小数字电路的面积。一个采用这种结构的4阶的数字滤波器在CYCLONE II FPGA芯片中被实现,耗费的硬件资源比Hogenauer结构的滤波器减少近29%。     

基于Matlab的FIR带通滤波器设计及DSP实现

借助Matlab的FDATOOL滤波器设计分析软件,设计了一种FIR数字带通滤波器,并对一段含噪语音信号进行滤波。利用汇编语言编程,在DSP上实现了该滤波器。实验结果表明,该数字带通滤波器精确,稳定性好,易于移植,具有很强的实用性与灵活性。     

不同阶数的FIR数字滤波器的DSP实现

在分析了FIR数字滤波器主要特点的基础上，采用最大误差最小化准则的等波纹迫近法，来设计FIR数字滤波器。然后通过Matlab程序设计语言中Remez函数扣Remezord函数计算FIR数字滤波器的系数，并基于美国德州仪器公司生产的TMS320C5402芯片的数字信号处理功能，应用DSP汇编语言编程实现了该滤波器，使不同阶数的FIR数字滤波器都可以用Matlab所得到的结果来修改DSP程序中的数据子程序。     

Digital Filter Design Using Computer Algebra Systems

Digital filter design can be performed very efficiently using modern computer tools. The drawback of the numeric-based tools is that they usually generate a tremendous amount of numeric data, and the user might easily lose insight into the phenomenon being investigated. The computer algebra systems successfully overcome some problems encountered in the traditional numeric-only approach. In this paper, we introduce an original approach to algorithm development and digital filter design using a computer algebra system. The main result of the paper is the development of an algorithm for an infinite impulse response (IIR) filter design that, theoretically, is impossible to be implemented using the traditional approach. We present a step-by-step procedure which includes derivations of closed-form expressions for (1) the transfer functions of the implemented digital filter which contains the algebraic loop; (2) the closed-form expression for computing the number of requested iteration steps; and (3) the error function representing the difference of the output sample values of the new filter and that of the conventional filter. We demonstrate how one can use some already-known multiplierless digital filter as a start-up filter to design a new digital filter whose passband edge frequency can be simply moved by using a single parameter. As a result, we obtain a multiplierless IIR filter, which belongs to the family of low-power digital filters where multipliers are replaced with a small number of adders and shifters.     

Multiplication-free adaptive digital filters

The authors update delta modulation digital filter weights using the LMS (least-mean-squares) and the SIGN algorithms to realize an adaptive digital filter without multiplication operations. It is shown that using the SIGN algorithm results in an adaptive filter that can be implemented using the simple up/down counting operations. Learning curves demonstrating convergence properties of the algorithms for a system identification problem are presented     

TD-SCDMA中FIR滤波器的DSP实现

文中首先说明了TD-SCDMA标准中对FIR滤波器的性能要求.同时以TD-SCDMA中的FIR滤波器为例,说明了数字滤波器的基本原理,讨论了如何应用MATLAB进行数字滤波器的设计,以及数字滤波器的DSP实现的基本思想,在实现过程中与MATLAB的结合.针对TI公司TM320C55X系列芯片进行汇编语言设计,平衡了设计精度和存储空间的要求,具有占用存储空间少,运行速度快的优点,更好地适应实时滤波的场合.     

多频带数字滤波器的设计和FPGA实现

本文介绍了一种应用于FPGA芯片的多频带数字滤波器的快速高效的设计、验证和实现的方法,该方法不同于传统的FPGA滤波器设计而且十分实用能大大缩短开发周期。首先根据多频带数字滤波器的性能要求,介绍了在具体性能指标下的多频带数字滤波在FPGA中实现的思想和原理,接下来描述了FPGA数字滤波器的传统设计方法和MATLAB设计方法,解释了采用极小化极大准则对滤波器的频率响应进行逼近的原理,然后结合一个具体的多频带数字滤波器的设计,给出了利用MATLAB进行多频带滤波器设计的过程以及HDL代码的生成步骤,最后介绍了该多频带滤波器在Modelsim中的RTL级仿真和在FPGA芯片中的门级实现。     

MATLAB-DSP集成环境下的FIR数字滤波器设计

文章介绍了有限冲激响应（FIR）数字滤波器的原理,以及如何根据工程中所给的参数设计所需的FIR数字滤波器。在MATLAB环境下完成FIR数字滤波器的设计与分析,利用CCSIDE完成数字滤波器的实现,通过CCSLink这一高效的工具完成MATLAB与DSP之间的实时数据传送,在不影响DSP运行的情况下完成DSP的开发。利用这一技术可以快速地对DSP进行控制与调试,极大地缩短了DSP的开发周期,提高了DSP的开发效率。     

Digital Filters for Real-Time ECG Signal Processing Using Microprocessors

Traditionally, analog circuits have been used for signal conditioning of electrocardiograms. As an alternative, algorithms implemented as programs on microprocessors can do similar filtering tasks. Also, digital filter algorithms can perform processes that are difficult or impossible using analog techniques. Presented here are a set of real-time digital filters each implemented as a subroutine. By calling these subroutines in an appropriate sequence, a user can cascade filters together to implement a desired filtering task on a single microprocessor. Included are an adaptive 60-Hz interference filter, two low-pass filters, a high-pass filter for eliminating dc offset in an ECG, an ECG data reduction algorithm, band-pass filters for use in QRS detection, and a derivative-based QRS detection algorithm. These filters achieve real-time speeds by requiring only integer arithmetic. They can be implemented on a diversity of available microprocessors.     

Design of digital impacting filter in CP-EBPSK with random-polar communication system

To solve the difficulty of designing digital impacting filter in the receiver of random-polar modulated Extended Binary Phase Shift Keying with Continuous Phase (CP-EBPSK), a design method based on Quantum-behaved Particle Swarm Optimization (QPSO) algorithm is proposed. Firstly, QPSO is introduced elaborately, and the basic flow of QPSO is also given. Then, the demodulation principle of digital impacting filter in the communication system of CP-EBPSK with random-polar is demonstrated, and QPSO is utilized to design the digital impacting filter, which also takes the effect of finite word length into consideration when implemented by hardware. Finally, the proposed method is simulated. Simulation results show that the digital impacting filter designed by new method can derive satisfied demodulation performance.     

一种数字下变频抽取滤波器的设计

对一个针对数字下变频应用的抽取滤波器从设计指标到版图实现的设计过程进行了详细介绍.该抽取滤波器实现了20倍的降采样,由CIC滤波器、CIC补偿滤波器和半带滤波器三级依次串联而成.通过利用抽取滤波器的等价变换和多项分解性质,各滤波器级的硬件电路开销和运行功耗都得到了降低.     

一种简单的多用途数字信道化结构

基于带通滤波器组的均匀数字信道化结构原型,根据软件无线电的模块化设计思想,提出了一种易于硬件实现的简单多功能数字信道化结构。能够实现2种抽取倍数:K=M和K=2M(K为信道数,M为抽取倍数)和2种滤波器组排列方式:偶型和奇型,两两组合形成的4种信道化结构。该结构针对不同信道化结构的要求,通过灵活配置模块,易于可编程门阵列(Field-Programmable Gate Arracy,FPGA)硬件实现。     

高速数传系统中成形滤波器的研究

介绍了高速数据传输系统中的频谱成形技术,研究了成形滤波器的参数确定和实现方法。提出了一种应用FPGA设计实现数字成形滤波器的方法。     

FPGA-based fully digital controller for three-phase shunt active filters

This article presents a fully digital controller for a three-phase shunt active filter. The harmonic isolator and the current controller both have been implemented in only one Field Programmable Gate Array (FPGA). This article discusses the design and implementation of digital hybrid modulated hysteresis current controller and multi-variable filters for shunt active filter controlling. Simulation and experimental results based on ‘FPGA in the loop’ prototyping demonstrate the effectiveness of the proposed fully digital controller.     

FIR数字滤波器的FPGA实现研究

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能．在Xilinx ISE10．1开发平台中,采用VerilogHDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构。并在ModelSim仿真验证平台中仿真了实现设计。结果表明,改进串行结构的实现消耗资源少但滤波速度慢．并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少。