高温退火非掺杂磷化铟制备半绝缘材料

对液封直拉(LEC)非掺磷化铟(InP)进行930℃ 80h的退火可重复制备直径为50和75mm的半绝缘 (SI)衬底.退火是在密封的石英管内纯磷(PP)或磷化铁(IP)两种气氛下进行的.测试结果表明IP-SI InP衬底具有很好的电学性质和均匀性,而PP-SI的均匀性和电学参数都很差.在IP-SI样品的PL谱中出现与深缺陷有关的荧光峰.光激电流谱的测量结果表明:在IP气氛下退火获得的半绝缘磷化铟中的缺陷明显比PP-SI磷化铟的要少.并对退火后磷化铟中形成缺陷的机理进行了探讨.     

高温退火非掺杂磷化铟制备半绝缘材料

对液封直拉(LEC)非掺磷化铟(InP)进行930℃ 80h的退火可重复制备直径为50和75mm的半绝缘 (SI)衬底.退火是在密封的石英管内纯磷(PP)或磷化铁(IP)两种气氛下进行的.测试结果表明IP-SI InP衬底具有很好的电学性质和均匀性,而PP-SI的均匀性和电学参数都很差.在IP-SI样品的PL谱中出现与深缺陷有关的荧光峰.光激电流谱的测量结果表明:在IP气氛下退火获得的半绝缘磷化铟中的缺陷明显比PP-SI磷化铟的要少.并对退火后磷化铟中形成缺陷的机理进行了探讨.     

Dislocation-free undoped semi-insulating GaAs epilayers prepared by chloride chemical vapor deposition and successive wafer annealing

Dislocation-free (DF) undoped semi-insulating GaAs epilayers have been realized by chloride chemical vapor deposition and successive wafer annealing. It was found that undoped conductive DF GaAs epilayers grown on Si-doped n-type DF GaAs substrates can be converted to semi-insulating by wafer annealing at temperatures higher than 950°C. The resistivity of these semi-insulating epilayers was higher than 10⁷ Ωcm. The outdiffusion of Si from the substrate to the epilayer was analyzed by secondary ion mass spectrometry and it was found that the thickness of the outdiffusion region was only 1μm.     

Effect of annealing conditions on the uniformity of undoped Semi-Insulating InP

Recently, it was found that undoped semi-insulating InP can be obtained by highpressure annealing of high purity materials. The reproducibility and the uniformity was, however, not satisfactory. In the present work, we found that not only Fe concentrations but also Cr and Ni concentrations in annealed wafers were slightly increased during annealing. Since it seems that the origin of the contamination was due to the vapor source of red phosphorus, conductive InP with a trace amount of Fe was annealed under low phosphorus vapor pressure in order to reduce the contamination. By preventing the contamination of Cr and Ni, preparation of semi-insulating InP became highly reproducible. The minimum Fe concentration for realizing semi-insulating InP was found to be 1 x 10¹⁵cm⁻³. It was also found that the better resistivity uniformity can be obtained at higher annealing temperatures.     

Deep centers in undoped semi-insulating InP

Undoped semi-insulating (SI) InP samples, subjected to one-step and multi-step wafer annealing, and lightly and normally Fe-doped SI InP samples without annealing have been characterized by thermally stimulated current (TSC) spectroscopy. A dominant deep center at 0.63 eV is found in all samples and is undoubtedly due to iron. Two prominent TSC traps, T_b (0.44 eV) and T_d (0.33 eV), found in undoped SI InP, are thought to be related to the phosphorus antisite P_In, and traps at low temperatures, like T_e* (0.19 eV), to the phosphrus vacancy V_P.     

Compensation mechanisms in nominally undoped semi-insulating InP and comparison with undoped InP grown under stoichiometry control

Nominally undoped semi-insulating InP can be prepared reproducibly by annealing under controlled phosphorus pressure. We present the electrical properties of a large series of undoped InP samples before and after annealing. Spectroscopic investigations show that the specimens are contaminated by iron during annealing, but native defects have to be taken into consideration in order to explain the electrical data. Annealed InP specimens are characterized by electrical and optical measurements and the results are compared to those obtained from InP crystals grown under stoichiometry control by the horizontal gradient freeze technique.     

Control of low fe content in the preparation of semi-insulating InP by wafer annealing

A reproducible technique for preparing semi-insulating (SI) InP by high temperature annealing can only be achieved by controlled doping with Fe in a sufficient concentration for compensation. However, a successful and reproducible method to adjust the low Fe content has not been developed up to now. In this paper, we report two different experimental approaches to control the Fe content by using either precompensated starting material or an Fe source for doping via the vapor phase. InP wafers (2′ diam) which were lightly predoped with Fe ([Fe] < 5 × 10¹⁵ cm⁻³) during liquid encapsulated Czochralski (LEC) growth were converted from the semiconducting to the SI state and were subsequently analyzed by laterally resolved resistivity measurements. These wafers show high resistivity uniformity (p ≈1 × 10⁸ Ω-cm) which has never previously been achieved with LEC material at such a low Fe concentration. Furthermore, we present the first results of annealing nominally undoped InP with a defined Fe source.     

Uniformity of deep levels in semi-insulating InP obtained by multiple-step wafer annealing

The uniformity of deep levels in semi-insulating InP wafers, which have been obtained by multiple-step wafer annealing under phosphorus vapor pressure, was studied using the thermally stimulated current (TSC) and photoluminescence (PL) methods. Only three traps related to Fe, T₀ (ionization energy E_i=0.19 eV), T₁ (0.25 eV), and T₂ (0.33 eV), probably forming complex defects, were observed in the wafer and they exhibited a relatively uniform distribution. PL spectra relating to phosphorus vacancies observed in some regions of the wafer are correlated with a small TSC signal having an ionization energy of 0.43 eV.     

Low-Temperature III–V Direct Wafer Bonding Surface Preparation Using a UV-Sulfur Process

A technique for direct wafer bonding of III–V materials utilizing a dry sulfur passivation method is presented. Large-area bonding occurs for GaAs/GaAs and InP/InP at room temperature. Bulk fracture strength is achieved after annealing GaAs/GaAs at 400°C and InP/InP at 300°C for times less than 12 h without large compressive forces. X-ray photoelectron spectroscopy measurements of the treated, bonded, and subsequently delaminated surfaces of GaAs/GaAs confirm that sulfide is present at the interface and that the oxide components show a reduced concentration when compared with samples treated with only an oxide etch solution.     

The use of atmospheric pressure MOVPE for the growth of high performance uncooled 1300 nm DFB lasers

Manufacture of high performance uncooled 1300 nm distributed feed-back (DFB) lasers operating single mode over the −40 to +85°C range requires control of the wavelength variation across a 2″ wafer to less than 10nm and preservation of grating definition during processing and regrowth. We have used atmospheric pressure metalorganic vapor phase epitaxy, without substrate rotation to achieve the necessary uniformity. Material was assessed using photoluminescence, x-ray diffraction, transmission electron microscopy, electrochemical current/voltage profiling, and secondary ion mass spectroscopy. The devices are based on a strained quantum well structure with an n-type grating layer to provide gain coupling. The best result gave a wavelength spread across 32×32 mm center square of a 2″ InP wafer of 3 nm. Buried heterostructure DFBs manufactured with high yield in this way operate from −40 to +85°C, with thresholds at 85°C as low as 18 mA.     

半绝缘InP的铁掺杂激活与电学补偿

比较了掺Fe和非掺退火半绝缘(SI)InP材料中Fe杂质的分布,掺杂激活机理以及Fe原子与点缺陷的相互作用.原生掺Fe SI-InP中Fe的替位激活主要通过填隙-跳跃机制,但Fe原子易在位错周围聚集,与空位形成复合体缺陷,占据填隙位等,从而降低Fe的激活效率.在FeP2气氛下退火非掺InP获得的SI-InP材料中,Fe原子的激活主要通过扩散过程的"踢出-替位"机制.退火前材料中存在的In空位使Fe原子通过扩散充分占据In位,同时抑制了材料中深能级缺陷的形成.因此,这种SI-InP材料的Fe激活效率高、电学性能好.     

Hg-Cd-Te phase diagram determination by high pressure reflux

A High Pressure Reflux technique has been used for the determination of pressure-temperature phase diagram data for the Hg-Cd-Te system in the pressure range of 9 to 98 atm. For elemental liquid Hg, the variation of vapor pressure with temperature is found to be represented by:ln P_Hg(atm) = 11. 270−7, 149/T (°K) for 789 ≤ T≤1O71°K, which is in good agreement with earlier determinations. The latent heat of vaporization of Hg calculated from this expression is 14. 155 kcal/g-at. For Hg-Te binary melts, the variation of vapor pressure is also found to be in good agreement with data obtained by vapor phase spectroscopy measurements. For pseudobinary Hg_1−xCd_xTe melts, the vapor pressure P at the liquidus temperature varies from 33 atm for x = 0. 20 to 74 atm for x = 0. 60. For these melts, it is found that the activity of Hg, a_Hg = P/P_Hg is constant with an average value of 0. 345 ± 0. 02 0, independent of x and T. The variation of vapor pressure over the pseudobinary melts is therefore represented by:lnP(atm) = 10. 206–7, 149/T (°K), for 0≤x≤ 0. 60 and     

Electrical properties of oxygen ion-implanted InP

The effect of oxygen ion implantation on defect levels and the electrical properties of undoped InP (n-type) and Sn-doped InP have been investigated as a function of postimplant annealing at temperatures of 300 and 400° C. The surface interruption by ion bombardment was studied by a non-invasive optical technique—photoreflectance (PR) spectroscopy. Current-voltage (I-V) characterization and deep level transient spectros-copy (DLTS) were carried out. The free carrier compensation mechanism was studied from the microstructure behavior of defect levels associated with O+ implantation. Free carriers may be trapped in both residual and ion-bombardment-induced defect sites. Rapid thermal annealing (RTA) performed at different temperatures showed that if residual traps were removed by annealing, the compensation efficiency will be enhanced. Post-implant RTA treatment showed that at the higher temperature (400°C), trapped carriers may be re-excited, resulting in a weakened compensation. Comparing the results of undoped and Sn-doped InP indicated that the carrier compensation effect is substrate doping dependent.     

An optimal annealing technique for ohmic contacts to ion-implanted n-layers in semi-insulating indium phosphide

An optimal annealing process was developed for sintering AuGe ohmic contacts to ion-implanted semi-insulating InP substrates. Contacts were annealed using a standard furnace, graphite strip heater and a lamp annealer. Alloying at 375°C for 3 min was found to be most suitable for achieving good contact morphology and lowest contact resistivity. Of the three techniques, the lamp annealing technique was found to give the best results when contacts were annealed under a SiO₂ cap. Contact resistivity as low as 8 × 10⁻⁶ cm² was obtained for ion-implanted n⁺ layers in semi-insulating InP.     

Surface cracking in Zinc diffused CdTe

CdTe slices have been diffused in sealed silica capsules under conditions of saturated vapor pressure due to zinc in the temperature range 390–950°C. All slices annealed with zinc at temperatures above 450°C displayed extensive surface cracking both by slip along specific crystallographic planes and by brittle fracture, whereas below this temperature no such effects were detected. In addition, some slices diffused at 800°C with small quantities of zinc, which was insufficient to maintain saturated vapor pressure throughout the diffusion experiment, did not show any cracks. The interpretation of this behavior can be divided into three temperature ranges and can be explained in terms of the critical resolved shear stress and the misfit ratio. This is discussed extensively in this paper.     

退火处理后非掺磷化铟的电传输特性

利用变温霍尔和电流-电压特性(I-V)两种方法分别对半导体和半绝缘的退火非掺磷化铟材料进行了测量.在非掺退火后的半导体磷化铟样品中可以测到缺陷带电导,这与自由电子浓度较低、有一定补偿度的原生非掺磷化铟的情况类似.非掺SI-InP表现出不同于原生掺铁的SI-InP的I-V特性,在一直到击穿为止的外加电场范围内呈欧姆特性,而掺铁SI-InP的I-V具有与陷阱填充有关非线性特征.根据空间电荷限制电流的理论,这种现象可以解释为非掺SI-InP中没有未被电子占据的空的深能级缺陷.     

Physico-chemical properties of Ga and In dopants during liquid phase epitaxy of CdxHg1−xTe

This work deals with the study by means of radioactive tracers and autoradiography, as well as measuring of galvanomagnetic properties, of Ga and In doping of epitaxial Cd_xHg_1−xTe layers during their crystallization from a Te-rich melt. Ga and In were introduced in the form of Ga⁷² and In¹¹⁴ master alloys with Te. The effective distribution coefficients of Ga and In during the crystallization of the Cd_xHg_1−xTe solid solutions with x=0.20 to 0.23 were determined by cooling the Te-base melt to 515–470°C. Depending on the concentration of the dopants and the time-temperature conditions of Cd_xHg_1−xTe growth, these ratios for Ga and In were 1.5–2.0 and 1.0–1.5, respectively. The electrical activity of Ga and In was determined after annealing of the Cd_xHg_1−xTe layers in saturated Hg vapor at 270–300°C. In doping of the epitaxial layers to (3–8)×10¹⁴ cm⁻³ with subsequent annealing in saturated Hg vapor at ∼270°C increases the carrier lifetime approximately by a factor of two as compared with the undoped material annealed under the same conditions.     

1990 Electronic Materials Conference

Silicon doped epitaxial layers of InP have been prepared by low pressure metalorganic chemical vapour deposition, using disilane as the source of silicon. Trimethylindium and phosphine were used as the source reactants for the growth. The doping characteristics for the epitaxial growth were investigated at substrate temperatures in the range 525–750° C and for doping levels in the range 4 × 10¹⁶−2 × 10¹⁹ cm⁻³. The results indicated that the Si doping level is proportional to the disilane flow rate. The Si incorporation rate increases with temperature, but becomes temperature-independent forT > 620° C. Comparison between Si concentrations determined by Secondary Ion Mass Spectroscopy, donor levels determined by Hall effect measurements, and optical measurements at 7 K indicates that approximately 50% of the Si in the InP is in the form of electrically inactive species. Uniform doping over 5 cm wafer dimensions has been obtained for growth atT = 625° C.     

Reactions between Pd thin films and InP

The reactions between Pd thin films and (001) oriented InP have been studied in detail. Palladium was deposited on InP by electron beam evaporation to a thickness of 60 nm. Specimens were then annealed in vacuum at temperatures up to 500° C for as long as several days. An amorphous ternary phase (Pd≈₃InP) formed during deposition. During annealing, several crystalline ternary phases were detected. Pd₂InP and Pd₅InP were detected at lower annealing temperatures,i.e. from 225–275° C. Pd₂InP grew first, exhibiting an epitaxial relationship with InP, followed by preferred growth of Pd₅InP within the Pd₂InP layer. Both phases later decomposed (≈400° C) producing Pd₂InP(II), which also grew epitaxially on InP. At temperatures greater than 400° C, Pd₂InP(II) decomposed to Pdln and PdP₂, which were thermodynamically stable in contact with InP.     

Development of wafer annealing for semi-insulating InP

Semi-insulating (SI) InP is becoming more and more important not only for high frequency devices such as HEMTs and HBTs but also for opto-electronic devices such as laser diodes and photodetectors in optical fibre communication systems with high data transmission rate exceeding 40 Gbs⁻¹. This trend needs high-quality SI InP, especially with extremely low Fe concentrations. Japan Energy Corporation (following on the tradition of Nippon Mining) has developed a commercially applicable wafer annealing process to prepare SI InP for this purpose.