磁性量子元胞自动机功能阵列的实验研究

采用电子束光刻、热蒸镀和剥离工艺在室温下制备了多组磁性量子元胞自动机器件功能阵列. 实验研究了曝光剂量和曝光时间对三个不同间距参数磁性量子元胞自动机阵列图案的影响, 发现100 pA电子束束流和0.38 μs曝光时间可获得理想的阵列图案. 对制备的反相器阵列结构进行了磁力显微测试, 结果显示了正确的逻辑功能, 成功实现了不同间距参数功能阵列的实验制备. 此外, 实验还发现纳磁体阵列制备中容易出现缺陷, 模拟结果表明丢失纳磁体缺陷导致了信号传递反相.     

基于多铁纳磁体的择多逻辑门三维磁化动态特性研究

建立了多铁纳磁体择多逻辑门的三维磁化动态模型,并施加应变时钟(应力或电压)对多铁择多逻辑门的择多计算功能进行了动态仿真,同时分析了应变时钟工作机制以及它与择多逻辑门可靠转换之间的关系.仿真结果表明所建三维动态模型准确地描述了择多逻辑门的工作机制,在30 MPa应力作用下,择多逻辑门接受新输入实现了正确的择多计算功能.研究还发现对中心纳磁体和输出纳磁体依次撤去应变时钟时,提前撤去输出纳磁体上的应力会降低择多逻辑门的正确计算概率,而延迟撤去输出纳磁体上的应力会降低择多逻辑门的工作频率.研究结果深化了人们对多铁择多逻辑门动态特性的认识,可为多铁逻辑电路的设计提供重要指导.     

磁性量子元胞自动机拐角结构的理论模拟和实验

磁性量子元胞自动机拐角结构是一种同时含有铁磁耦合和反铁磁耦合的电路. 理论模拟了外加时钟场作用下铸铁磁性材料拐角结构的信号传递. 采用微磁仿真给出了信号传递的磁化演化图, 结果证实了铸铁纳磁体能够实现含有两种冗长耦合结构的稳定转换. 实验制备了相应的拐角结构, 扫描电子显微图和磁力显微图结果显示了成功的电路图案和正确的两种耦合方式信号传递.     

基于概率模型的量子元胞自动机加法器容错性能研究

采用概率转移矩阵方法和电路分割理论建立了两种结构的量子元胞自动机 (QCA)加法器的容错性模型, 深入分析了各组成元件对加法器的整体容错性能的影响. 指出元件在较低的正确概率时, 传输线对整体正确概率影响较小, 而当元件正确概率较高时, 传输线的正确概率对整体正确概率的影响急剧增大, 并且在整个参数变化范围内反相器始终是影响整体正确概率的主要元件. 采用Frobenius范数对两种同一功能不同结构的QCA加法器的整体容错性能进行了比较, 发现由5输入择多逻辑门构成的QCA加法器的整体容错性能优良. 这对于目前QCA加法器的容错性设计以及今后大规模QCA电路的容错性设计具有重要意义.     

基于多铁逻辑的铁磁耦合互连线磁化动态模拟

建立了多铁纳磁体逻辑器件的铁磁耦合作用模型,通过施加应变时钟对铁磁耦合互连线的磁化动态进行了理论模拟.结果表明:合适的应力(19.7—20.1 MPa)能够实现近180?磁化翻转,完成逻辑态在铁磁耦合互连线中的正确传递;多铁纳磁体间的强耦合阻碍器件的有效磁化翻转,这可能源于小间距增强了纳磁体的面外磁化,从而阻碍了面内翻转.研究结论可为多铁逻辑电路的设计提供重要指导.     

基于倾斜纳磁体翻转倾向性的与(或)逻辑门应力模型

纳米磁性逻辑器件具有高抗辐射性、低功率、天然非易失性等优势,应用前景广阔.倾斜放置的纳磁体具有翻转倾向性,在控制时钟撤去后倾斜纳磁体倾向于翻转至长轴的一端.利用倾斜纳磁体的翻转倾向性,提出了一种应力调控的与(或)磁逻辑门,并建立了其动态磁化的数学模型.使用微磁学方法对逻辑门进行了仿真,结果验证了预期逻辑门功能.与现有的逻辑门相比,基于倾斜纳磁体的与(或)门结构具有能耗更低、可靠性更高和制造工艺更简单等优点.     

考虑公交港湾式停靠的多速混合城市交通流元胞自动机模型研究

在Nagel-Schreckenberg提出的元胞自动机模型基础上,建立了考虑公交车辆和港湾式公交停靠站的多速混合车辆单车道城市交通流元胞自动机模型.通过计算机模拟,给出了随机减速概率、混合车流密度、公交车辆平均停靠时间、公交车辆占有率和港湾式公交车站间距对混合车流速度和流量的影响图.对混合车流的特性进行了分析和讨论. 关键词： 元胞自动机 港湾式公交停靠站 混合交通流模型 计算机模拟     

基于交换作用的纳磁逻辑电路片上时钟结构研究

纳磁逻辑电路具有低功耗、非易失和可常温下制备等优点, 实现低功耗片上时钟是其集成化的必备条件. 本文提出了一种基于交换作用的纳磁逻辑电路片上时钟结构, 用载流铜导线产生的奥斯特场将铁磁体薄膜覆层进行磁化, 然后依靠铁磁体层与纳磁体界面存在的交换作用场使后者磁化方向发生翻转. 与轭式铁磁体时钟用外磁场控制纳磁体磁化方向相比, 该方案在功耗方面降低了5/6, 时钟边界杂散场强度降低了2/3, 达到降低功耗、减轻串扰的目的. 此外, 采用微磁仿真进一步验证了该时钟结构上的纳磁体逻辑阵列可以实现逻辑功能. 关键词： 纳磁逻辑 片上时钟 交换作用     

物理型硬件木马失效机理及检测方法

对两种物理型硬件木马造成芯片退化或失效的机理进行了详细分析. 通过使用ATLAS 二维器件仿真系统并结合SmartSpice电路逻辑仿真器, 模拟了两种物理型硬件木马对反相器逻辑电路输出特性的影响. 使用ATHENA工艺仿真系统模拟了掺杂离子注入工艺过程, 实现了掺杂型硬件木马的金属-氧化物-半导体场效应管(MOSFET)器件; 使用热载流子注入退化模型对ATLAS 仿真器件进行热载流子压力测试, 以模拟热载流子注入型硬件木马注入MOSFET器件并造成器件退化失效的过程, 分别将上述掺杂型硬件木马和热载流子注入型硬件木马的MOSFET器件与另一个正常MOSFET器件组成同样的反相器逻辑电路. 反相器使用Spice 逻辑电路仿真输出DC直流、AC瞬态传输特性以研究物理型硬件木马对电路输出特性的影响. 为了研究MOSFET器件的物理特性本身对硬件木马的影响, 在不同温度不同宽长比(W/L)下同样对反相器进行Spice电路逻辑输出仿真. 本文分析了离子掺杂工艺、热载流子注入压力测试形成的物理型硬件木马随压力强度、温度的变化对逻辑电路输出特性的影响. 通过结果对比分析得出了含有物理型硬件木马的逻辑电路在DC直流输出特性上的扰动比AC瞬态传输特性更明显的结论. 因此, 本文提出了一种针对物理型硬件木马的检测流程. 同时, 该检测流程是一种具有可操作性的检测物理型硬件木马的方法.     

复合元胞自动机系统反向迭代加密技术研究

提出了元胞自动机的交叉复合在序列R下随机复合的思想,分析了复合元胞自动机系统的密码学特性,利用元胞自动机反向迭代加密技术,构造了两个基于复合元胞自动机的密码系统.新的复合元胞自动机密码系统很好地解决了单一元胞自动机密码系统中存在的误差单向扩散的问题,并且能够以较小的规则半径获得大密钥空间.计算机仿真结果表明,复合元胞自动机密码系统具有良好的扰乱和扩散性能,能够有效地抵抗蛮力攻击和差分分析. 关键词： 离散动力系统 复合元胞自动机 反向迭代 分组密码     

Exploring the thermodynamic limits of computation in integrated systems: magnetic memory, nanomagnetic logic, and the Landauer limit

Nanomagnetic memory and logic circuits are attractive integrated platforms for studying the fundamental thermodynamic limits of computation. Using the stochastic Landau-Lifshitz-Gilbert equation, we show by direct calculation that the amount of energy dissipated during nanomagnet erasure approaches Landauer's thermodynamic limit of kTln(2) with high precision when the external magnetic fields are applied slowly. In addition, we find that nanomagnet systems behave according to generalized formulations of Landauer's principle that hold for small systems and generic logic operations. In all cases, the results are independent of the anisotropy energy of the nanomagnet. Lastly, we apply our computational approach to a nanomagnet majority logic gate, where we find that dissipationless, reversible computation can be achieved when the magnetic fields are applied in the appropriate order.     

Photonic logic NOR gate based on two symmetric microring resonators

We demonstrate an all-optical NOR logic gate based on symmetric GaAs-AlGaAs microring resonators whose resonances are closely matched. Two input pump data streams are tuned close to one resonance of the symmetric microrings to switch a probe beam tuned to another resonance by two-photon absorption. The switching energy of the gate is 20 pJ/pulse, and the switching window is 40 ps, limited by the carrier lifetime. The use of two rings provides for better cascading in photonic logic circuits because of the higher number of available ports.     

Parity checking and generating circuit with semiconductor optical amplifier in all-optical domain

In this paper, an all-optical parity checker and parity generator circuit is proposed in which SOA-MZI configuration is used to implement the XOR logic gate. This performance monitoring logic device is simulated at ultra high speed i.e. 120 GHz. Two logic circuits are proposed for parity generator, in one design inverter used to generate parity bit is implemented by the same additional XOR gate as inverter while in 2nd design inverter is implemented using XGM in SOA and thus number of SOA in 2nd design is reduced. ER ratio achieved in 1st case is 9.28 with maximum Q factor 73.39 and minimum BER 0 while in 2nd design it is 9.35 with maximum Q factor 8.41 and minimum BER 1.93e−17. ER ratio achieved in parity checker circuit is 32.54 with maximum Q factor 77.76 and minimum BER 0.     

Amorphous silicon logic integrated circuits

Amorphous silicon thin-film integrated circuits, with between 4 and 18 transistor functions per chip, have been fabricated on glass substrates. The amorphous silicon and the dielectric layers are deposited by rf glow discharge. The circuits have been designed to realize basic logic functions such as inverters, NAND and NOR gates, and addressable memory cells. For the first time, an amorphous silicon flip flop requiring a supply voltage of only 4.5 V has been manufactured. The logic voltage levels of the flip flop are compatible with standard bipolar TTL circuits. Measurements on an inverter chain show a typical propagation delay time of 70 s and a power-delay-time product of 65 pJ. All of the circuits use n-channel enhancement type load transistors instead of integrated ohmic load resistors. The channel length of the driver transistors is 15 m with a gate source/drain overlap of 7.5 m. Experimental geometry ratios range from =2.25 to =21. Generally, the driver transistors exhibit on/off ratios greater than 10⁶ for supply voltages smaller than 5 V. At these voltages the measured on-currents per unit channel width are in the order of 5...10nA/m.The influence of the geometry ratio on static inverter characteristic and switching speed is discussed by means of a simple model. Two different manufacturing schemes for the fabrication of the integrated circuits are outlined. Mask layouts and experimental transfer characteristics of several integrated circuits are presented.     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

基于碳纳米管场效应管构建的纳电子逻辑电路

展示了由碳纳米管场效应管构成的三种逻辑电路，分别为单个p型碳纳米管场效应管的开关电路、由集成在同一片硅片上的单个p型碳纳米管场效应管和单个n型掺氮碳纳米管场效应管构成的互补型反相器，以及两个独立的p型碳纳米管场效应管构成的或非门. 其中p型碳纳米管场效应管以单壁碳纳米管作为沟道，而n型碳纳米管场效应管则以掺氮的多壁碳纳米管作为沟道，器件的源漏电极均为铂电极. 关键词： 碳纳米管 场效应管 逻辑电路