A low distortion CMOS continuous‐time common‐mode feedback circuit

In high‐gain fully differential operational amplifier (FD op‐amp) design, the output common‐mode (CM) voltage of the FD op‐amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common‐mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuous‐time CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded‐cascode op‐amp and the other is the Multiply‐by‐Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog‐to‐digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

The design and implementation of a multi‐wing chaotic attractor based on a five‐term three‐dimension system

The last two decades have seen great progress about the generation and circuit realization of multi‐wing chaotic attractor. In this paper, several multi‐scroll chaotic attractors are generated from a five‐term system by adding a piecewise linear function. Moreover, some basic properties in terms of symmetry and dissipation, equilibrium points, eigenvalues of the Jacobian matrices, Lyapunov exponent spectrum, bifurcation diagram, and Poincaré map are studied. In particular, an analog circuit is designed to implement the proposed multi‐scroll attractors, which are different from the traditional attractors. Furthermore, an integrated circuit diagram is designed to realize the fractional‐order multi‐scroll attractors. Finally, the performed experimental results confirm the theoretical analysis, and our work lends itself to many potential applications in engineering. Copyright © 2015 John Wiley & Sons, Ltd.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

Non-linear op-amp circuits: Existence and uniqueness of solution by inspection

Even simple circuits containing only one op amp and linear resistors can have multiple d.c. operating points. Using a realistic non-linear d.c. op-amp model which includes the saturation characteristics, this paper gives the necessary and sufficient conditions for an arbitrary op-amp circuit (containing op amps, linear resistors, strictly-increasing non-linear resistors and independent sources) to have a unique solution for all values of circuit parameters. These conditions are remarkable because they are couched strictly in topological terms. For many op-amp circuits (e.g. those containing only one op amp), the necessary and sufficient conditions can be checked by inspection.     

Designing non-linear single OP-AMP circuits: A cook-book approach

The inherent saturation non-linearity of the op amp is used to design circuits having a wide variety of useful non-linear v-i characteristics. These circuits are made of one op amp and 3 or 4 linear resistors which are passive under a rather mild assumption derived from the 3-port paramountcy condition. Explicit design formulae are given for each prototype circuit and numerous examples are given and validated by actual measurements.     

Performance evaluation and experimental analysis of a novel single‐phase brushless PM motor

In order to equip the single‐phase brushless permanent magnet (PM) motor with self‐starting capability without a complex structure, we present a new kind of asymmetric air‐gap topology which can lead to the d‐ , q ‐axis magnetic circuit asymmetry of the motor. The field‐circuit‐coupling finite element method simulation model of the proposed motor controlled with a constant V / f control is built by using the 2D Maxwell software. The geometric parameters of the motor are also optimized by changing pole arc ratio of the PM (α_p ) and its eccentricity (e ), and the operational characteristic is investigated. Finally, an experimental platform of the prototype and its control system are set up. Performance comparison of the experimental results and simulation results of the proposed motor running in various operating modes is reported. All the results show that the asymmetric air‐gap single‐phase brushless PM motor has potential to be used in the household appliances. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A single‐stage integrated bridgeless AC/DC converter for electrolytic capacitor‐less LED lighting applications

In this paper, a single‐stage integrated bridgeless AC/DC converter is proposed. As compared to its counterpart that is composed of totem‐pole boost power factor correction (PFC) cascade fly‐back DC/DC converter, the studied circuit has less components number while overcoming the limits of the totem‐pole type. Thus, it is suitable to the low‐power LED lighting applications. Furthermore, when both PFC inductors L_b and magmatic inductance L_m of the transformer TR1 operate at discontinuous current mode, the bus voltage v_CB can be used to decouple the ac input and constant dc output power. Thus, the approach of increasing bus voltage ripple is employed to eliminate electrolytic capacitors and obtain long operation lifetime. Additionally, it is able to be compatible with our studied twin‐bus configuration for increasing the overall efficiency. A 50‐W hardware prototype has been designed, fabricated, and tested in the laboratory to verify the proposed converter validity. Copyright © 2014 John Wiley & Sons, Ltd.     

MOS‐integrable circuitry for multi‐scroll chaotic grid realization: A SPICE‐assisted proof

A MOS‐integrable circuit realization of the class of Multi‐Scroll Grid attractor using an implementation of nonlinear transconductor is presented. The design can be seen as the MOS‐integrable circuit implementation of modified jerk equations presented in the literature (Int. J. Bifurcat. Chaos 2002; 12 (1):23–41). The proposed design of Multi‐Scroll Grid attractor is adequately supported by SPICE simulation results. Copyright © 2008 John Wiley & Sons, Ltd.     

Application of duality principle to synthesis of single‐stage power‐factor‐correction voltage regulators

The duality principle is applied to derive new single‐stage power‐factor‐correction (PFC) voltage regulators. This paper begins with an application of duality transformation to conventional discontinuous‐conduction‐mode buck, buck‐boost and boost converters. The resulting dual converters operate in the discontinuous capacitor voltage mode. These new converters provide the same PFC property, but in the dual manner. It is proved that in the practical case of the input being a voltage source, the mandatory insertion of inductance between the voltage input and the ‘dual PFC converter’ does not affect the power‐factor‐correcting property. A new single‐stage PFC regulator is derived by taking the dual of a well‐known circuit based on a cascade of conventional boost and buck converters. Analytical design expressions are derived, illustrating the relation between current stress and component values. Experiments are performed to confirm the operation of the circuit and its power‐factor‐correcting capability. Copyright © 2003 John Wiley & Sons, Ltd.     

Output‐feedback model‐reference adaptive calibration for map‐based anti‐jerk control of electromechanical automotive clutches

It is well known that the map‐based control can reduce the computational burden of the automotive on‐board controller. This paper proposes an output‐feedback model‐reference adaptive control algorithm to calibrate the map‐based anti‐jerk controller for electromechanical clutch engagement. The algorithm can be used to adaptively construct a data‐driven fuzzy rule base without resorting to manual tuning, so that it can overcome the problem of conventional knowledge‐based fuzzy logic design, which involves strenuous parameter‐tuning work in the construction of calibration maps. To accurately define the consequent of each fuzzy rule for anti‐jerk control, an output feedback law for computing the reference trajectory of clutch engagement is developed to eliminate the discontinuous slip‐stick transition, whereas an adaptive controller is designed to track the reference trajectory and compensate the nonlinearity. The convergence of the proposed output‐feedback model‐reference adaptive control algorithm is analyzed. Simulation results indicate that the proposed method can successfully reduce the excessive vehicle jerk and frictional energy dissipation during clutch engagement as compared with the conventional knowledge‐based fuzzy logic controller without fine tuning.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

The CCII+ and the ICCII as basic building blocks in low‐pass filter realizations

Three new grounded capacitor current mode low‐pass filters using two inverting second‐generation current conveyor (ICCII) or one double output ICCII are given. The circuits employ the minimum number of passive circuit components, namely two resistors and two capacitors. The circuits are generated from three new voltage mode low‐pass filters realized with the ICCII. A new grounded capacitor CCII+ current mode low‐pass filter is generated from one of the new voltage mode low‐pass filters employing two ICCII?. A new grounded passive component low‐pass filter with independent control on Q and using three ICCII+ is also introduced. Spice simulation results based on using the 0.5 µm CMOS model are included to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.     

Low‐voltage rail‐to‐rail switched buffer topologies

This paper presents some CMOS rail‐to‐rail low‐voltage (1.2 V) switched buffer topologies, to be used as input stages in switched‐opamp circuits. The main buffer is based on the use of an op‐amp featuring rail‐to‐rail input and output swing with constant transconductance over the input common mode voltage. The designed buffer exhibits a total harmonic distortion of about ‐61 dB for 5 MHz clock frequency with 2 V_pp input amplitude. Its characteristics have been compared with those of other rail‐to‐rail switched buffers, based on the main CMOS OTA (simple, symmetrical, Miller), showing good distortion even at frequencies in the MHz range and satisfying the requirements for the series switches. Copyright © 2001 John Wiley & Sons, Ltd.     

Positive‐real property of passive fractional circuits in W‐domain

Fractional circuits have attracted extensive attention of scholars and researchers for their superior performance and potential applications. Fractional circuits constitute a new challenge for the analysis and synthesis methods of traditional circuits theory. Passivity is the fundamental property of traditional circuits (integer order electric circuits). As is known to all, passivity is equivalent to positive realness in traditional linear circuits. However, this equivalence is broken down by introducing fractional elements into electrical networks in s‐domain. To address this issue, on the basis of s‐W transformation, we study the passive criteria of fractional circuits with rational order elements in this paper. Definitions of positive‐real (matrix) function in W‐domain are given, and the equivalence conditions of positive realness are derived. In addition, a conclusion is proposed in which the immittance (matrix) function of passive fractional circuits with rational order elements is positive real in W‐domain. The applications of passive criteria in circuit synthesis are shown.     

Towards analog implementations of PWL two‐dimensional non‐linear functions

This paper deals with the circuit implementation of non‐linear algebraic bivariate functions. The synthesis procedure is based on a piecewise‐linear approximation technique and on a corresponding circuit architecture, whose basic element is a circuit block with the input/output function y(x) = max(0; x). Some known CMOS circuit structures that can be used to obtain such a block are considered, and their main advantages and drawbacks are pointed out. The static and dynamic features of both the single circuit block and the overall architecture for two‐dimensional PWL functions are illustrated by way of examples. Copyright © 2005 John Wiley & Sons, Ltd.     

Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐μW power consumption at 1.2‐V supply.     

A 5‐MHz AT‐cut quartz crystal oscillating circuit functioning in 350 nA

An oscillating circuit functioning at ultra low power (350 nA) for a 5‐MHz AT‐cut quartz crystal oscillator was investigated. This circuit has a resistance between the power terminal of the CMOS‐IC and the power supply, and another between the earth terminal of the CMOS‐IC and the ground (GND). These resistances discourage an inrush of current, and set a gain (g_m) necessary for oscillating the circuit at minimum. The developed circuit is quite simple, but enables driving at once‐unthinkable, low power (below 1 µA). © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n‐dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three‐variate static functions and one concerning a dynamical control system defined by a bi‐variate PWL function. Copyright © 2009 John Wiley & Sons, Ltd.     

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

Frequency compensation of a multistage operational amplifier (op‐amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op‐amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two‐stage and three‐stage op‐amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well‐known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed‐loop poles and zeros of the op‐amp. Intuitive graphical design procedures for two‐stage and three‐stage op‐amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three‐stage op‐amp in a standard 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. With a load capacitance of 500 pF, post‐layout simulations show that the op‐amp achieves a low‐frequency gain of 144 dB, a phase margin of 58^°, and a unity‐gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8‐V supply voltage. Comparisons with the published amplifiers show that our op‐amp achieves the figure of merits comparable to those of the state of the art. Copyright © 2015 John Wiley & Sons, Ltd.     

90dB‐DR 3.3V CMOS single‐ended‐to‐fully differential and fully differential‐to‐single‐ended amplifiers for audio applications

This paper presents the design and the realization of single‐ended‐to‐fully differential and fully differential‐to‐single‐ended amplifiers to be used in an audio signal processing system. The proposed blocks allow to reduce significantly the pin number of the developed system, while guaranteeing the high quality (16bit) performance required in an audio channel. The proposed circuits have been realized in a standard 3.3V 0.35 µm CMOS technology and achieve a Dynamic Range in excess of 90dB with a Total Harmonic Distortion lower than ‐80dB for a full scale signal amplitude. Their power consumption (≈6mW and each) and the area (0.1mm² each) are finally negligible with respect to the other blocks in the overall systems. Copyright © 2003 John Wiley & Sons, Ltd.