一种全差分的高速CMOS运算跨导放大器(OTA)的优化设计

全差分高速CMOS运算跨导放大器由一个折叠-级联输入级和一个共源输出增益级构成，并采用Cascode补偿技术．在对运算跨导放大器的性能做了详细的分析后，设计出一个采用单纯形优化算法的优化程序，它能够快速地设计出满足指标的运算跨导放大器．最后给出了一个设计实例．     

1.9GHz低电压低功耗CMOS射频低噪声放大器的设计

针对1.9GHzPHS和DECT无线接入系统的应用,提出了一种可工作于0.9V低电压的CMOS射频低噪声放大器,并对其电路结构、噪声及线性度等主要性能进行分析。该电路基于传统的折叠结构低噪声放大器,利用晶体管线性补偿技术,实现了低压低功耗下的高线性度。采用TSMC 0.18μm CMOS工艺模型设计与验证。     

低功耗低噪声CMOS放大器设计与优化

分析了两种传统的基于共源共栅结构的低噪声放大器LNA技术:实现噪声优化和输入匹配SNIM技术并在功耗约束下同时实现噪声优化和输入匹配PCSNIM技术。针对其固有不足,提出了一种新的低功耗、低噪声放大器设计方法。     

Operator‐based robust control for nonlinear plants with uncertain non‐symmetric backlash

This paper presents an operator‐based robust nonlinear control method for nonlinear plants with uncertain non‐symmetric backlash. The control design is achieved by introducing operator‐based robust right coprime factorization. In more detail, using an operator‐theoretic approach, the uncertain non‐symmetric backlash is described as a generalized Lipschitz operator and a bounded parasitic term. Since the generalized Lipschitz operator is unknown, a new robust condition using robust right coprime factorization is proposed to guarantee robust stability of the controlled plant with the uncertain backlash. As a result, based on the proposed robust condition, a stabilized plant is obtained. For eliminating the effect from the parasitic term to ensure the output tracking performance, a nonlinear tracking controller is designed. Simulation results are presented to validate the effectiveness of the proposed control design method. Copyright © 2010 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society     

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is an emerging nanotechnology, potentially suitable to replace the popular technologies like Complementary Metal Oxide Semiconductor (CMOS) technology. The evolution of QCA has become prominent due to high operating frequency, nanoscale device and zero current low power nanotechnology. However, the Area-Delay-Energy aware QCA logic circuit design remains a prime concern in this post CMOS technology. In this work the primary attention is given to build efficient QCA circuits. The motivation of this work is to propose Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product). Different methodologies are reported to design a combinational and sequential circuit in QCA technology. An extensive focus is given in designing of 3 different QCA based Area-Delay-Energy aware SRAM memory cells, parallel read/write M × N SRAM memory array and peripherals like decoder and multiplexer. Since appropriate signal distribution network (SDN) is an essential aspect to deign QCA circuit, it has also been reported a delay aware signal distribution methodology applicable for any type of QCA logic circuit design. The significant results of this research finding are expressed in terms of Area-Delay-Energy dissipation tradeoff. When compared with respective to the state of art, the performance metric of proposed QCA based memory cells are excelled, on an average 40% reduction in area, 33% and 22% drop in delay and energy dissipation respectively are achieved for proposed three different memory cell design.     

Tensor semantic model for an audio classification system

Audio resources are a very important part of multimedia information.The classification effect of audio is directly related to the service mode of personal resource management systems.At present,vector features have been widely used in audio classification systems.However,some semantic correlations among different audio information can not be completely expressed by simple vector representation.Tensors are multidimensional matrices,and their mathematical expansion and application can express multi-semantic information.The tensor uniform content locator(TUCL) is proposed as a means of expressing the semantic information of audio,and a three-order tensor semantic space is constructed according to the semantic tensor.Tensor semantic dispersion(TSD) can aggregate some audio resources with the same semantics and,at the same time,its automatic classification can be accomplished by calculating the TSD.In order to effectively utilize TSD classification information,a radial basis function tensor neural network(RBFTNN) is constructed and used to train an intelligent learning model.Experimental results show that the tensor model can significantly improve the classification precision under multi-semantic classification requests within an information resource management system.     

Efficient design of SIW filters by using equivalent circuit models and calibrated space‐mapping optimization

This article presents a very efficient technique for the design of filters in substrate‐integrated waveguide (SIW) technology. The proposed design approach is based on the combined use of equivalent circuit models of SIW discontinuities and a “calibrated” space‐mapping optimization technique. The effectiveness of this design technique is demonstrated through some examples. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.     

抗辐射低噪声CMOS图像传感器设计技术研究

为满足航天应用对大面阵高动态CMOS图像传感器的需求,对噪声优化与辐射加固等关键技术进行了深入研究。基于系统架构的增益级与双相关双采样设计优化、基于采样电路的时序改进,实现了对系统噪声的多层次优化;基于像素级与电路级的总剂量辐射加固与单粒子闩锁辐射加固设计,实现了对100k rad(Si)总剂量和99.8 MeV·cm2/mg单粒子效应的免疫。研究成果已成功应用于一款64M像素超大面阵高性能CMOS图像传感器产品。流片测试结果显示,抗总剂量辐射能力优于100k rad(Si)、暗电流与噪声随辐射增长率提升了一个数量级;抗单粒子闩锁能力优于99.8 MeV·cm2/mg;在整个辐射环境下读出噪声不超过5e-;本征动态范围高达75dB。     

一种新型CMOS电流控制电流传输器

提出了一种基于共源共栅电流镜的CMOS电流控制电流传输器(CCCⅡ)电路。该电路由跨导线性环电路和共源共栅电流镜构成。相对于基于基本电流镜的CMOS电流控制电流传输器,该电路具有输出阻抗更大以及电流传输精度更高的优点。分析了电路的工作原理,给出了实验结果,验证了电路的正确性。     

一种超宽带低噪声放大器

提出一个共源共栅结构的超宽带低噪声放大器。该电路基于台积电0.18μmCMOS工艺,工作在3GHz～5GHz频率下,用来实现超宽带无线电。仿真结果表明,该低噪声放大器有最大13.6dB的增益。整个频段噪声系数小于1.9dB。输入和输出反射损耗都小于-11dB。一阶压缩点在-15dBm左右。功耗为18.7mW。     

Analysis of CMOS 0.18 μm UWB low noise amplifier for wireless application

Microsystem Technologies - In this work, a 0.18 μm CMOS LNA is designed which is favorable for a wireless application and the topology used in this design is cascode inductive source...     

Multifingers capacitances modeling of 65‐Nm CMOS transistor by unit cell method

The multifingers' parasitic capacitances modeling of 65‐nm CMOS transistors for millimeter‐wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high‐frequency structure simulator environment. The material properties of the devices as given by the foundry are used during simulation and then full electromagnetic simulations are carried out to extract the Y‐parameters of the model. Unit‐cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit‐cells and then the parasitic capacitances of the unit‐cells are calculated from the extracted Y‐parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error). © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2012.     

基于gm/ID参数的运算放大器设计

介绍一种基于gm/ID参数特性的模拟电路优化设计方法,并以CMOS密勒补偿运算放大器的设计为例具体阐述该方法的基本设计步骤.该方法以统一的gm/ID与ID/(W/L)的关系曲线为基本设计出发点,综合电路的其它设计要求,而提出的一种优化性能指标的设计思路.对所设计的运算放大器模拟仿真验证了这种方法的有效性.     

LMI optimization approach to robust decentralized controller design

A new approach for design of robust decentralized controllers for continuous linear time‐invariant systems is proposed using linear matrix inequalities (LMIs). The proposed method is based on closed‐loop diagonal dominance. Sufficient conditions for closed‐loop stability and closed‐loop block‐diagonal dominance are obtained. Satisfying the obtained conditions is formulated as an optimization problem with a system of LMI constraints. By adding an extra LMI constraint to the system of LMI constraints in the optimization problem, the robust control is addressed as well. Accordingly, the decentralized robust control problem for a multivariable system is reduced to an optimization problem for a system of LMI constraints to be feasible. An example is given to show the effectiveness of the proposed method. Copyright © 2010 John Wiley & Sons, Ltd.     

Application of bacteria foraging algorithm for the design optimization of multi‐objective Yagi‐Uda array

The design of antenna array with desirable multiple performance parameters such as directivity, input impedance, beam width, and side‐lobe level using any optimization algorithm is a highly challenging task. Bacteria Foraging Algorithm (BFA), as reported by electrical engineers, is the most robust and efficient algorithm in comparison with other presently available algorithms for global optimization of multi‐objective, multi‐parameter design problems. The objective of this article is to apply this new optimization technique, BFA, in the design of Yagi‐Uda array for multi‐objective design parameters. We optimize length and spacing for 6 and 15 elements array to achieve higher directivity, pertinent input impedance, minimum 3‐dB beam width, and maximum front to back ratio both in the E and H planes of the array. At first, we develop a Method of Moments code in MATLAB environment for the Yagi‐Uda array structure for obtaining the above design parameters and then coupled with the BFA for the evaluation of the optimized design parameters. Detail simulation results are included to confirm the design criteria. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2010.     

Synthesis of thinned concentric circular antenna arrays using teaching‐learning‐based optimization

In this article, the design of thinned concentric circular antenna arrays (CCAAs) of isotropic radiators with optimum side lobe level (SLL) reduction is studied. The newly proposed global evolutionary optimization method; namely, the teaching‐learning‐based optimization (TLBO) is used to determine an optimum set of turned ON elements of thinned CCAAs that provides a radiation pattern with optimum SLL reduction. The TLBO represents a new algorithm for optimization problems in electromagnetics and antennas. It is shown that the TLBO provides results that are somewhat better than those obtained using other evolutionary algorithms, like the firefly algorithm and biogeography based optimization. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:443–450, 2014.     

Post micromachining of MPW based CMOS–MEMS comb resonator and its mechanical and thermal characterization

In recent years micro electro mechanical system (MEMS) based micro resonant sensors have been given a lot of attention due to their potential as a platform for the development of many novel physical, chemical, and biological sensors. That is why this paper covers post processing of the structures fabricated through Multi-Project-Wafer using 0.35 µm MIMOS CMOS technology with particular focus on dry etching of Si and SiO₂ from the front side of CMOS–MEMS chip that is optimized using aluminum coated carrier wafer and achieved results are debris free as compared to photoresist coated carrier wafer. The device is etched through from the front side to avoid parasitic capacitances and squeeze film damping by keeping minimum size of the die. The etching of SiO₂ as well as deep Si etch-through using the same plasma etcher (SS110A Tegal) is successfully demonstrated in this work. Finally, after the successful post CMOS micromachining of the device, resonance frequency i.e. 8164 Hz and quality factor i.e. 51.34, is determined. The joule heating effect due to the passing of current through the central shuttle of the device is characterized. The maximum temperature close to the anchors of the comb resonator where the piezoresistors are located is determined through temperature coefficient of resistance measurement using PE-4RF type probe station and it is found to be 37.62 °C.     

Microbenchmarks for determining branch predictor organization

In order to achieve an optimum performance of a given application on a given computer platform, a program developer or compiler must be aware of computer architecture parameters, including those related to branch predictors. Although dynamic branch predictors are designed with the aim of automatically adapting to changes in branch behavior during program execution, code optimizations based on the information about predictor structure can greatly increase overall program performance. Yet, exact predictor implementations are seldom made public, even though processor manuals provide valuable optimization tips. This paper presents an experimental flow with a series of microbenchmarks that determine the organization and size of a branch predictor using on‐chip performance monitoring registers. Such knowledge can be used either for manual code optimization or for design of new, more architecture‐aware compilers. Three examples illustrate how insight into exact branch predictor organization can be directly applied to code optimization. The proposed experimental flow is illustrated with microbenchmarks tuned for Intel Pentium III and Pentium 4 processors, although they can easily be adapted for other architectures. The described approach can also be used during processor design for performance evaluation of various branch predictor organizations and for testing and validation during implementation. Copyright © 2004 John Wiley & Sons, Ltd.     

A broadband hybrid GaN cascode low noise amplifier for WiMax applications

This article reports a Microstrip design for low noise amplifier (LNA) using a packaged commercial GaN‐on‐SiC high electron mobility transistor (HEMT). A cascode configuration with an inter‐stage matching and an independent biasing technique was used. A lumped elements design was first developed, analyzed, and simulated in ADS. Then the design was implemented using microstrip technology and simulated using the momentum EM simulation in ADS. The LNA is easy to fabricate, has a low cost, and can be easily modified for other applications. The proposed GaN LNA showed a gain of 13.5 dB with a noise figure (NF) of 3 dB from 2.8 to 3.8 GHz.     

Inverse modeling for fast design optimization of small‐size rat‐race couplers incorporating compact cells

In the paper, a framework for computationally‐efficient design optimization of compact rat‐race couplers (RRCs) is discussed. A class of hybrid RRCs with variable operating conditions is investigated, whose size reduction is obtained by replacing ordinary transmission lines with compact microstrip resonant cells (CMRCs). Our approach employs a bottom‐up design strategy leading to the development of compact RRCs through rapid design optimization of its building blocks and a subsequent fine tuning to account for parasitic cross‐coupling effects. The fundamental component of the proposed method is an inverse CMRC surrogate model, covering a wide range of cell electrical parameters, and enabling a convenient adjustment of coupler bandwidth. Having the surrogate model established, it is possible to produce close‐to‐optimum CMRC dimensions at a negligible computational cost. The subsequent correction step requires only up to two electromagnetic simulations of the CMRC. The proposed method is demonstrated by designing an RRC for several operational bandwidths. Experimental results are also provided.