On-Die Power Supply Noise Measurement Techniques

This paper presents techniques for characterizing wide-band on-chip power supply noise using only two on-chip low-throughput samplers. The properties of supply noise and their associated measurement techniques are reviewed to show how this can be achieved. An initial design of the samplers uses high-resolution VCO-based analog-to-digital converters, and experimental results from a test-chip verify the efficacy of the measurement techniques. To enable simple sampler designs to be used even in aggressively scaled process technologies, measurement systems based on dithered low-resolution samplers are also developed and experimentally characterized.      

On-die droop detector for analog sensing of power supply noise

Understanding the supply fluctuations of various frequency harmonics is essential to maximizing microprocessor performance. Conventional methods used for analog validation of the power delivery system fall short in one or more of the following areas. 1) Measurement accuracy in both frequency and time domains, especially for very high-frequency noise caused by large di/dt events. The multigigahertz power supply noise attenuates very quickly away from the die. Conventional approaches of measuring the noise at the pins of the package or at the die using capacitive probes are not accurate for multigigahertz clocks. For this reason, the observability of high-frequency on-die noise has been very tricky. 2) Implementation (e.g., delivery) of analog references to multiple areas across a "noisy" die, compactness/modularity of the measurement units, restraining assumptions inherent in the measurement circuit such as periodicity of the supply noise event. 3) Automation to enable a timely volume of measurements. The efficiency of the measurements is key to correlating a particular speed path to poser supply noise. To address these issues, this paper presents an on-die droop detector (ODDD), a scalable IC solution implemented and validated on a 90-nm process, for analog sensing of differential high-bandwidth supply noise.     

Partial EBG Structure with DeCap for Ultra‐wideband Suppression of Simultaneous Switching Noise in a High‐Speed System

To supply a power distribution network with stable power in a high‐speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uniplanar compact electromagnetic bandgap (UC‐EBG) structure is well known as a promising solution to suppress the power noise and isolate noise‐sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC‐EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.     

低噪声、低功耗CMOS电荷泵锁相环设计

设计了一种 1 .8V、0 .1 8μm工艺的低噪声低功耗锁相环电路 ,其采用 CSA(Current Steer Amplifier)架构的压控振荡器 (VCO)。整个电路功耗低 ,芯片面积为 1 60 μm× 1 2 0 μm,对电源和衬底噪声抑制能力强。经过Spice模拟表明 ,在有电源噪声的情况下 ,输出 5 0 0 MHz时钟时周对周抖动小于 41 ps,功耗为 2 .8m W,最终与芯片的量测结果基本一致     

直放站多种供电电源的监控系统设计

直放站在通信系统中十分重要,是一种中继产品,其质量好坏的衡量指标包括技术服务、整机是否可靠、低噪音系数、低IP3、智能化水平等。为了更好地发挥直放站的作用,需要创建监控系统,用于监控其电源质量。文中设计的监控系统,其控制核心为LPC1768,该处理器为嵌入式,能够对直放站中的多种供电电源进行监控。配合隔离ADC电路,可以实时监控直流供电与交流供电的电源质量。该监控系统能够同时完成和多接口通道的配合,并把供电数据传输到网管平台,使用平台对数据进行分析,从而达成直放站设备供电状况的实时监控、提前预警,以防电源质量问题给直放站造成不良影响,确保供电系统的安全与稳定。     

数字音频D类功放电源误差校正方法研究

为了实时校正供电电源噪声引起的数字音频D类功放输出误差,提出一种基于FPGA的电源误差校正方法。使用高精度ADC芯片将电源纹波信号转化为数字量后送入FPGA,校正模块根据电源纹波的大小对数字音频D类功放Sigma-Delta调制器输入值进行预校正处理,从而实现在功放输出端有效的抑制电源噪声。经过实际电路测试,该方法可以有效的抑制电源噪声对数字音频D类功放的影响,电源抑制比达到36.78 dB。     

Measurement of VLSI power supply current by electron-beam probing

The measurement of power supply noise and current by electron-beam probing is described. Noise measurements can be made on the chip under test, and current measurements can be made on the circuit board. It is noted that power supply voltages are obtained simultaneously. This measurement method is particularly useful when combined with a larger program of circuit characterization, or design verification, by electron-beam probing     

单片CMOS UHF RFID阅读器中低噪声LC VCO的设计

设计了一种应用于单片CMOS超高频射频识别阅读器中的低功耗、低相位噪声LC VCO。根据超高频射频识别阅读器的系统架构和协议要求,对本振相位噪声要求做出详细讨论;采用LC滤波器和低压差调压器分别对尾电流源噪声和电源噪声进行抑制,提高了VCO相位噪声性能。电路采用IBM 0.18μm RF CMOS工艺实现,电源电压3.3 V时,偏置电流为4.5 mA,中心频率为1.8 GHz,在频偏1 MHz处,相位噪声为-136.25 dBc/Hz,调谐范围为30%。     

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

采用LMS算法消除开关电源对CDMA接收机的影响

研究了开关电源开关频率对CDMA接收机的影响,拟提高开关电源的应用领域。分析了开关电源的噪声及常用抑制噪声的方法。通过Simulink建立CDMA通信系统模型,以单频正弦为噪声干扰CDMA接收机,并利用自适应陷波器和LMS算法在接收机基带处进行处理。处理前后误码率、EVM值均有不同程度的下降。该方法为开关电源在射频领域的应用提供了基础,且具有良好的应用前景。     

CMOS LC-oscillator phase-noise analysis using nonlinear models

In this paper, a second-order stochastic differential equation is used as a tool for the analysis of phase noise in a submicron CMOS LC oscillator. A cross-coupled topology typical of integrated CMOS designs is considered. Nonlinear limiting and mobility degradation effects in the circuit are modeled and used to predict the statistics of the random amplitude and phase deviations in terms of design variables. Assuming Gaussian noise disturbances and describing the phase noise as a random diffusion process, the average phase-noise power spectrum is derived and its accuracy verified with measurement and simulation results. Calculations for phase noise arising from stationary tank noise, nonstationary channel thermal noise, and flicker noise are discussed. The analysis is used to emphasize the fundamental power/performance tradeoff associated with compensation of tank losses via adjustments in the power supply and device size.     

直流电源输出的纹波和噪声的测量

对于直流电源纹波和噪声的测量,不同的测量方法测量的结果往往差别较大。针对这个问题,本文先介绍了电源输出的纹波和噪声的基本概念,并在此基础上介绍了三种常见的纹波和噪声的测量方法：直接测量的方法、去掉探头和探头接地线的测量方法和使用同轴电缆的测量方法。通过分析、比较,阐明了不同测量方法之间的区别,明确了对示波器的要求及测量的注意事项,以使大家能够根据具体情况选用适宜、方便的测量方法,准确地测量到直流电源输出的纹波和噪声。     

Measurement of PLL phase error caused by power supply noise

The measurement of the accumulated phase error of phase-locked loops (PLLs) in microprocessor systems is discussed. A system which creates controlled power supply noise and measures the PLL response is described. Examples of the use of this technique are shown for a PLL used in a 400 MHz microprocessor     

通信电源常用仪测设备简介

通信电源质量稳定与否,对整个通信网络系统的稳定、畅通至关重要,直接影响到通令的安全和通信质量。为了通信网络的良好运行,必须保证供电各项技术指标符合规定要求。正确运用检测设备,有利于提高通信电源品质。文章对通信电源设备制造和使用中常用的测量仪器如示波器、数字万用表、电参数测试仪、高低频噪声测试仪、交直流数字钳型表、红外线测温仪、接地电阻测试仪、功率谐波分析仪和抗扰性试验仪器等进行了介绍。     

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed.The relevant parameter analysis and the details of circuit design are presented.The test chip was implemented in a TSMC 0.18μm 1P4M RF CMOS process.The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz.The measured noise figure is around 1.5-1.7 dB on both bands.The LNA consumes less than 4.3 mA of current ...     

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

An in situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in product-level LSIs, was developed. The design of the on-chip voltage sampling probe is based on a simple ring oscillator, which converts local supply difference between VDD and V_SS to oscillation-frequency deviation. High measurement accuracy is achieved by off-chip digital signal processing and calibration. This scheme was used to successfully measure 69-mV local supply noise with 5-ns time resolution in a 3G-cellular-phone processor. It will thus help in designing power-supply networks and in visually verifying the quality of a power supply     

Separation of the common-mode- and differential-mode-conducted EMInoise

A device is developed to decipher common-mode and differential-mode noise from a conducted EMI noise measurement. This device is a useful tool for power supply circuit noise diagnosis and line filter design     

5V单电源供电的低噪声宽带放大器

以单片机MSP430F449为控制核心,设计了一个5 V单电源供电的低噪声宽带放大器。采用单位增益稳定低噪声运放OPA820作为前级放大,高速运放THS3091作为末级放大,其中利用DC-DC变换器TPS61087将5 V电压转化为18 V从而为末级放大电路供电。此外,系统还采用12位高速A/D转换器ADS803实现了测量并数字显示放大器输出电压峰峰值的功能,测量误差小于5%。本系统最高电压增益达到43 dB,上限及下限截止频率达到15 MHz和20 Hz,在50Ω负载上,最大不失真输出电压峰峰值为4.2 V。系统的输出噪声小于200 mV。     

自跟踪陷波器

本文提出一种自动调谐陷波器,其陷波中心频率自动跟踪市电频率或某一外加干扰频率,以抑制其干扰.陷波器的谐振电路由LC组成,而电感L是用普遍阻抗转换器(GIC)来实现,GIC的端接电阻为压控MOS管电阻,因此可以用一电压控制此电阻以改变电感值,进而控制陷波频率.这种陷波电路可用于抑制市电频率的干扰噪声并防止测量或数据采集系统中前置放大器的饱和.实验结果表明在频率从4555Hz,其陷波频率跟踪精度优于0.5Hz,而陷波深度(串模抑制比)为3040dB.     

A Low-Power Self-Forward-Body-Bias CMOS LNA for 3–6.5-GHz UWB Receivers

A low-power low-noise amplifier (LNA) implemented in 0.18 $mu$m CMOS technology utilizing a self-forward-body-bias (SFBB) technique is proposed for UWB low-frequency band system. By using the SFBB technique, it reduces supply voltage as well as saves additional bias circuits, which leads to low power consumption of 4.5 mW with low supply voltage of 1.06 V for two drain-to-source voltage drops. The complementary architecture and direct coupling technique between the first two stages also save bias circuits. The measurement result shows that the proposed LNA presents a maximum power gain of 16 dB with a good input impedance matching (${rm S}11 < - 12$ dB) and an average noise figure of 2.65 dB in the frequency range of 3–6.5 GHz.