Preparation of n+ emitter on p-type silicon wafer using the spin-on doping method

There is a strong need for cost reduction in manufacturing crystalline silicon solar cells, and one of the approaches is to merge two steps of silicon wafer processing into one step without degrading the performance of solar cells. In this work, we intended to employ the spin-on doping (SOD) method for the purpose of dual tasks, phosphorus diffusion to form n⁺ emitters and antireflection coating (ARC) to reduce optical reflection. Different from the commercial SOD solutions based on SiO₂, we used tetraethylorthosilicate (TEOS) to prepare SOD solutions containing different concentrations of phosphorus acid as the phosphorus doping source. We first investigated the dependence of the sheet resistance of the n⁺ emitters on the concentration of phosphorus acid in the SOD solution as well as the thermal diffusion temperature and time. It was found that all these three factors can effectively influence the sheet resistance of the n⁺ emitters, suggesting a relatively easier optimization process for forming n⁺ emitters using the SOD method. The SOD thin films formed after the thermal diffusion process were found to be SiO₂ films. We then investigated the antireflection properties of the as-grown SOD thin films, and found that they can effectively reduce the optical reflection of silicon wafers.     

Ion-sensing devices with silicon nitride and borosilicate glass insulators

Ion-sensitive field-effect transistors (ISFET's) with silicon dioxide, silicon nitride, and borosilicate glass as the active gate material were fabricated and tested for pH-sensing applications. The borosilicate glass and silicon nitride devices were found to have a linear potential/pH response and previous theories of ISFET function were inadequate to explain this. A two-site theory is presented that can explain the features of the potential/pH response of both silicon nitride and borosilicate glass ISFETs. The model is easily extended to any two-site system.     

Properties of spin-on glass as an insulator for InP metal-insulator-semiconductor structures

The application of Futurrex IC1-200 spin-on glass as an insulator for InP metal-insu-lator-semiconductor (MIS) structures including InP MIS capacitors and InP MIS field-effect transistors (MISFET’s) was investigated. Preliminary measurements of the elec-trical properties of the spin-on glass were performed using Si MIS structures with the spin-on glass insulator layer. It was found that the spin-on glass which is subjected to a final curing treatment utilizing a rapid-thermal annealing at 600° C for 5 sec in a O₂ ambient exhibits the best electrical properties. However, it was demonstrated by sec-ondary ion mass spectroscopy that when done on InP, the 600° C rapid-thermal an-nealing resulted in the outdiffusion of indium and phosphorus into the spin-on glass. The change in the spin-on glass electrical characteristics due to this outdiffusion re-sulted in an instability in the InP MISFET operation.     

Thin-film devices fabricated with benzocyclobutene adhesive wafer bonding

In this paper, we present and elaborate on die to wafer bonding technology with benzocyclobutene (BCB). This technology allows to fabricate a variety of reliable waferbonded components in a fairly simple way using only standard cleanroom equipment. We demonstrate the fabrication of passive devices such as microring resonators, as well as active components such as lasers and LEDs. We show good performance of these devices by presenting measurements of their characteristics. Furthermore, these devices were subjected to damp-heat testing, demonstrating the good quality of the BCB-bonding procedure. Finally, due to the low thermal conductivity of BCB, thermal management needs some attention. We present an analysis of the thermal problem and suggest a possible solution.     

Anodic bonding of glass and silicon wafers with an intermediate silicon nitride film and its application to batch fabrication of SPM tip arrays

This paper reports a detailed study of wafer-level anodic bonding with a dielectric intermediate layer and its application to the fabrication of scanning probe microscope (SPM) probe arrays. First, the bonding performance between sodium-ion rich glass and silicon nitride coated silicon substrate is characterized. The effects of voltage, tool pressure, bonding time, surface properties, and cleanliness are thoroughly studied. Then, the silicon nitride based SPM probe arrays consisted of pyramidal tip and 1.5 μm-thickness cantilever are successful bonded and transferred to Pyrex 7740 glass substrate by use of our optimized wafer-scale electrostatic force bonding condition. The nano-imaging capability of the scanning probe array is also demonstrated.     

Microcavities with field emitters sealed by silicon wafer bonding

A method of fabricating micrometre-sized field emission diodes is described. The devices use silicon field emitters that have been grown by selective epitaxy into 0.9 mu m sized contact holes in a 1 mu m thick field oxide. The anode of the device structure is a silicon wafer directly bonded to the field oxide.<>     

JVD silicon nitride as tunnel dielectric in p-channel flash memory

High-quality jet vapor deposition nitride is investigated as a tunnel dielectric for flash memory device application. Compared to control devices with SiO₂ tunnel dielectric, faster programming speed as well as better retention time are achieved with low programming voltage. The p-channel devices can be programmed by hot electrons and erased by hot holes, or vice versa. Multilevel programming capability is shown     

Photoemission spectroscopy of heterojunctions of amorphoushydrogenated silicon with silicon oxide and nitride

A study of the growth and electronic structure of a-Si:H/a-SiN_x:H and a-Si:H/a-SiO_x:H heterojunctions by photoemission spectroscopy is discussed. The interfaces in a-Si:H/a-SiO_x are atomically abrupt, except for the SiO_x on the Si interface which is graded over ~3 Å due to plasma oxidation. The offset energies between the a-Si:H valence band and those of a-SiN_x:H and a-SiO_x:H are 1.2 and 4.0 eV, respectively. Extra H(~2×10¹⁵) is incorporated in the Si on the SiN_x interface region. The hole wave functions in a-Si:H are localized on a scale of 1-2 interatomic distances     

Bonding of silicon with filled and unfilled polymers based on black silicon

A bonding method for silicon wafers with unfilled and filled polymer components using `Black Silicon' is presented. The working principle is an interconnection of `Black Silicon' surfaces with ductile materials. Needles of nanostructured `Black Silicon' with their increased surface and undercut features penetrate the polymer when applying pressure. Plastic deformations of the polymer lead to a permanent bond. The retention force exceeds 1000 N/cm² as experiments with polypropylene and low temperature co-fired ceramic tapes (polymer filled with ceramic) show. The application areas are smart packaging, fluidic interconnects for microsystems, electronic assembly and hybrid polymer-ceramic silicon systems     

Tensile tests of micro anchors anodically bonded between Pyrex glass and aluminum thin film coated on silicon wafer

Micro anchor is a kind of typical structures in micro/nano electromechanical systems (MEMS/NEMS), and it can be made by anodic bonding process, with thin films of metal or alloy as an intermediate layer. At the relative low temperature and voltage, specimens with actually sized micro anchor structures were anodically bonded using Pyrex 7740 glass and patterned crystalline silicon chips coated with aluminum thin film with a thickness comprised between 50 nm and 230 nm. To evaluate the bonding quality, tensile pulling tests have been finished with newly designed flexible fixtures for these specimens. The experimental results exhibit that the bonding tensile strength increases with the bonding temperature and voltage, but it decreases with the increase of the thickness of Al intermediate layer. This kind of thickness effect of the intermediate layer was not mentioned in the literature on anodic bonding.     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

Deterioration of insulating films on silicon wafer due to surface charging during ion implantation

Charge-up phenomena during ion implantation were studied using the wafers (1) covered with the 1 μm thick photoresist and (2) fabricated with the MOS capacitor devices. The wafers were implanted with 35 keV As⁺ at the beam currents of 1 mA to 10 mA. The surface potential was measured by a capacitive probe set in the chamber. The ion distribution was also measured by a beam profile monitor placed behind the rotating disc. Surface charging on the photoresist wafers in some cases led to the puncture of the resist layer. Probe measurement showed that the charge-up phenomena were to a large extent governed by the behavior of the secondary electrons generated at ion implantation. The wafers with the MOS devices hardly failed by the charge build-up because of the bulk conduction through the thin oxide. However, the C-V measurement indicated that the deterioration of the oxide were influenced by the beam distribution.     

Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process

This work describes and discusses fast wafer level reliability (fWLR) Monitoring as a supporting procedure on productive wafers to achieve stringent quality requirements of automotive, medical and/or aviation applications. Examples are given for the various reliability topics: dielectrics, devices, metallisation, plasma charging with respect to required test structures, stress methods and data analysis. Application areas of fWLR are highlighted and limitations considered. Further aspects such as relevant reliability parameters, sampling strategies and out of control action plans are discussed.     

采用界面薄层氧化硅的硅片直接键合技术研究

本文研究了采用界面薄层氧化硅的硅片直接键合技术。利用原子力显微镜（AFM）和剪切力测试分别表征表面粗糙度和键合强度随着薄层氧化硅厚度的变化情况。对比了采用热氧化和等离子体增强化学气相沉积法（PECVD）两种方法对晶片粗糙度及键合强度的影响。结果表明采用热氧化和PECVD沉积薄层氧化硅做硅片直接键合,键合强度分别可以达到18MPa和8MPa,键合强度随着薄层界面氧化硅厚度的增加而下降,这对于MEMS器件制备及其他硅片直接键合的应用都具有十分重要的指导意义。     

Passivation of GaAs FET's with PECVD silicon nitride films ofdifferent stress states

The passivation of GaAs MESFETs with plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride films of both compressive and tensile stress is reported. Elastic stresses included in GaAs following nitride passivation can produce piezoelectric charge density, which results in a shift of MESFET characteristics. The shift of MESFET parameters due to passivation was found to be dependent on gate orientation. The experiments show that nitride of tensile stress is preferable for MESFETS with [011-bar] oriented gates. The shifts in V_TH,I_DSS, and G_M of the devices before and after nitride passivation are less than 5% if the nitride of appropriate stress states are used for passivation. The breakdown voltage of the MESFETs after nitride deposition was also studied. It is found that the process with higher hydrogen incorporation tends to reduce the surface oxide and increase the breakdown voltage after nitride deposition. In addition, the passivation of double-channel HEMTs is reported for the first time     

具有三层复合结构的P型硅外延片制备工艺研究

对10.16 cm(4英寸)三层复合结构P型硅外延片的制备工艺进行了研究。利用PE-2061S型桶式外延炉,在重掺硼的硅衬底上采用化学气相沉积的方法成功制备P~-/P~+/P/P~+型硅外延层。通过FT-IR(傅里叶变换红外线光谱分析)、C-V(电容-电压测试)、SRP(扩展电阻技术)等测试方法对各层外延的电学参数以及过渡区形貌进行了测试,最终得到结晶质量良好、厚度不均匀性<3%、电阻率不均匀性<3%、各界面过渡区形貌陡峭的P型硅外延片,可以满足器件使用的要求。     

Wafer-level packaging of silicon to glass with a BCB intermediate layer using localised laser heating

Adhesive wafer-level bonding is an excellent solution to meet the stringent requirements in micro-electro-mechanical systems (MEMS) packaging, one of the challenges in MEMS manufacturing, in a steadily growing micro-systems market. A range of bonding processes for commercially available substrate bonders have been developed, which apply global heating during the bonding procedure. This article, however, describes an approach where heating is kept to a minimum by combining the merits of laser joining, a truly localised heating technique, and adhesive wafer-level bonding. This unique bonding technique, which enables the use of temperature-sensitive materials within the package, is demonstrated for bonding of silicon to glass - materials commonly used in MEMS fabrication - with a benzocyclobutene (BCB) intermediate bonding layer. As a proof of concept for wafer-level packaging, bonding of two simplified patterns is demonstrated, one with five individual samples on the same wafer, and the other with nine samples. To verify the influence of this innovative bonding technique on the quality of the seal the devices are shear force tested and the results are compared with those of devices packaged at chip-level.     

Comparison of the open circuit voltage of simplified PERC cells passivated with PECVD silicon nitride and thermal silicon oxide

Plasma enhanced chemical vapor deposited silicon nitride films have been used to passivate both the front and rear surface of simplified PERC silicon solar cells (planar surface, single‐step emitter). An independently confirmed open circuit voltage (V_oc) of 667 mV was measured, proving the outstanding surface passivation provided by the silicon nitride films. The achieved V_oc represents a significant improvement for all‐SiN passivated silicon solar cells. A conversion efficiency of 17˙8% was obtained. For comparison, similar cells with different passivation schemes, including high quality, thermally grown TCA oxides and thin SiO₂/SiN double layers, were also investigated. Open circuit voltages up to 673 mV and conversion efficiencies up to 18˙3% were achieved. Copyright © 2000 John Wiley & Sons, Ltd.