Multistage monostable multivibrator using load-coupled regenerative feedback

A monostable multivibrator configuration using a new technique of regenerative feedback is discussed. This circuit provides an elegant alternative in situations wherein several monostable multivibrators have to be connected in tandem.     

Jitter reduction in self-sustaining monostable clock recovery circuit

A simple circuit modification is presented for reducing the output jitter of the self-sustaining monostable multivibrator clock recovery circuit. Jitter is reduced by preventing the monostable multivibrator from being triggered by pulses that arrive early. Experimental results in a fibre-optic system employing the Petrovic code show that, with this modification, the jitter variance can easily be reduced by a factor of 6.     

A self correcting clock recovery circuit

Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.     

A fast controlled monostable circuit using tunnel diodes

A circuit is developed for the identification of random events of single and paired pulses. The output pulse length of this "controlled monostable" circuit is proportional to the time interval of the paired pulses and the response to a single pulse is in the monostable mode.     

Simple TRAPATT circuit for 2nd-harmonic extraction

An efficient 2nd-harmonic-extraction coaxial TRAPATT oscillator is described. The oscillator consists of two low-impedance sections that essentially control the 2nd-harmonic load and reactive terminations. A peak power output of 25 W at 5.2 GHz is reported from an S band silicon p+?n?n+ TRAPATT diode.     

Simple square-rooting circuit using OTAs

A method to implement a square-rooting circuit is described. The proposed circuit employs operational transconductance amplifiers (OTAs) as the only active elements. The implementation technique is based on an electronically variable resistor formed by the OTA, where the magnitude of the resistance is controlled by the output current, to provide the square-rooting function. The proposed scheme can operate with both a voltage input and a current input signal. The purpose of the circuit is emphasised in terms of simple configuration, high accuracy and low cost. Experimental results showing the circuit performance are presented.     

Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

The monostable–bistable transition logic element (MOBILE) is a promising application for negative differential resistance (NDR) circuit. Previously reported MOBILE is constructed by resonant tunneling diode (RTD) that is implemented by the molecular beam epitaxy (MBE) process. However in this paper, we first propose a NDR circuit composed of standard Si-based metal–oxide–semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Then we demonstrate the inverter, NAND, and NOR gate operations using this MOS–HBT–NDR-based MOBILE circuit. The great advantage of this NDR-based application is that we can implement it using the standard SiGe BiCMOS process without the need for the MBE system.     

Novel wideband 2-18 GHz clock extraction circuit for optical transmission systems

A novel circuit technique that provides wideband clock extraction for digital regenerative repeaters is described. The scheme employs a closed loop electronically tuned YIG filter than can be locked to the fundamental or harmonics of the extracted clock.<>     

A performance analysis of all-optical clock extraction circuit based on stimulated Brillouin scattering

In this paper, we develop an analytical method to deal with the timing performance in an optical clock extraction circuit based on stimulated Brillouin scattering (SBS). Three kinds of SBS active filters are considered and their frequency-transfer functions are obtained under the assumption that pump depletion caused by SBS is negligible. When pump depletion is taken into account, an SBS active filter acts as a nonlinear filter. To investigate the timing performance at this situation, we introduce the concept of "dynamic frequency-transfer function" to describe its frequency-response property for a fixed-signal light and pump light. Using the obtained "frequency-transfer function," we give analytical expressions for both root-mean-square (rms) phase jitter and rms amplitude jitter of the extracted optical clock, in which we have taken the impacts of SBS gain, pump light linewidth, optical pulse chirp, and pump detuning into account. Finally, a detailed numerical investigation on the timing performance for the three active filters is presented.     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

All-optical timing extraction using an optical tank circuit

An ultrafast all-optical timing extraction method using an optical tank circuit is described, and experimental results at 2 Gb/s are reported. A Fabry-Perot resonator, whose free spectral range is equal to the clock frequency of the incoming optical data stream, is utilized as the optical tank circuit. Its fully passive structure and ultra-high-bit-rate operation (~Tb/s) is possible through decreasing resonator length     

A slew-rate controlled output driver using PLL as compensation circuit

A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-/spl mu/m CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variation over process, voltage, and temperature variation of the output driver. The constant delay time, which is generated by the replica of the voltage-controlled oscillator in the PLL, reduces the slew-rate variation over load capacitance variation. Such an output driver has 25% less variation at slew rate than that of the conventional output driver. The proposed output driver is able to meet UDMA100 interface that specifies load capacitance ranging from 15 to 40 pF and slew rate from 0.4 to 1.0 V/ns.     

All-optical timing extraction using a 1.5 μm self pulsatingmultielectrode DFB LD

All-optical timing extraction from an intensity modulated 196 Mbit/s return to zero optical data stream by the injection locking technique, using a 1.5 μm self-pulsating multielectrode DFB laser diode (LD) is demonstrated. A frequency lock-in range, which depends upon both the injection signal level and the length of space continuation is investigated     

Novel system clock generation from a modulated signal

This paper describes a novel technique to derive a pure-spectral system clock with a common multi-modulus divider from a frequency modulated signal. Therefore, the dividing factor is inverse frequency modulated to compensate the frequency modulation component on the divider input signal. Additionally, $\Upsigma\Updelta$ dithering is applied to the frequency divider. The technique is used for a FM-radio transmitter based on an all-digital phase-locked loop (PLL) to generate a higher-frequency clock for baseband signal processing. It can also be applied to other PLL based transmitters or receivers, especially, if only a slow PLL reference clock is available and a faster system or baseband clock is required. The main factor determining the quality of the generated clock signal is the PLL??s reference quartz oscillator as it determines the accuracy of the PLL??s RF oscillator, which limits then the accuracy of the newly generated clock. In the FM-radio transmitter, a generated ??1?MHz clock signal with 30.58?ppm frequency offset and 515?ps root mean square jitter is generated. The phase noise is determined to ?83.5?dBc/Hz at 10?kHz offset and ?70.5?dBc/Hz at 1?kHz, respectively. The signal can also be used in co-integrated or external circuits.     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

大幅度CCD输出信号降噪的相关双取样电路

电荷耦合器件(CCD)的输出信号构成复杂,包含有典型的KTC、1/f等类型的噪声,需要进行专门处理后才能获得与入射光信号相对应的高信噪比信号。文章针对具有较大幅度的CCD输出信号,采用宽电压工作的独立运放满足幅度较大的信号处理要求;通过在同一个运算放大器上实现噪声保持及信号采样的形式,消除了不同通道增益差异对信号的影响,获得了较高线性度的信号处理效果;同时结合CCD驱动器的设计,获取相关双取样技术所需的采样及保持脉冲信号,增强了采样与CCD输出信号间的关联程度,从而进一步提高了相关双取样技术消除CCD噪声的效果。采用这种信号处理电路后,将原来噪声处理的水平从约22 mV提高到了约1 mV,并且在一种精密的位移测量系统中得到应用,最后就具体电路设计的难点及注意事项进行了阐述。     

一种高精度双极性电流输出电路设计

电流电路由于其结构简单、抗干扰性强、安全性高和适合长距离传输等优点被广泛用于航空机载非电信号的机上传输,设计实现了一种双仪表放大器构造电流输出电路,支持-20～20mA的高精度恒流源输出,同时支持电压反馈及电流反馈两种实时监测,通过MutiSim仿真及实物测试,电流输出精度满足0.1%的设计要求,可用于机载设备的电流输出电路设计。     

基于放大反馈激光器高速全光时钟提取的研究

为了研究放大反馈激光器全光时钟提取的性能,采用单边带相位噪声功率谱积分的方法,对40Gbit/s无恶化信号和噪声恶化信号分别进行了时钟提取实验,计算了所提取时钟的时间抖动。同时还测量了放大反馈激光器的锁定范围。通过实验取得了恶化前后所提取时钟的时间抖动分别为130fs和150fs,放大反馈激光器的锁定范围为234MHz。结果表明,基于放大反馈激光器的全光时钟提取方案对噪声恶化具有较强的容忍度,而且具有较宽的锁定范围。这一结果对于全光时钟提取技术的进一步发展具有重要意义。