Defect generation in InGaN/GaN light-emitting diodes under forward and reverse electrical stresses

Electrical and optical degradations of GaN/InGaN single-quantum-well light-emitting diodes (LEDs) under high-injection current (150 A/cm²) and reverse-bias (−20 V) stresses were investigated. A substantial increase in the tunneling components of both forward and reverse currents was observed in the devices subjected to reverse biases. However, the stressed LEDs exhibited minimal degradation of optical characteristics. For devices subjected to high forward currents, a monotonic decrease in light intensities with stress time, accompanied by an increase of forward leakage current, was observed in the low-injection region, but a positive stress effect was found on the light output measured at high currents. These degradation behaviors can be explained by slow generation of point defects in the LEDs via different mechanisms, i.e., thermally induced defect formation in the InGaN active region in the devices subjected to high-injection currents, and destructive microstructual changes as a result of impact ionization in the cladding layer in the devices under high reverse-bias stress.     

Arsenic Junction Thermal Stability and High-Dose Boron-Pocket Activation During SPER in nMOS Transistors

In this letter, thermal stability of arsenic (As) junctions formed by solid-phase epitaxial regrowth and their impact on device performance are investigated. If the temperature does not exceed 800 degC, a 35% junction sheet-resistance improvement over the conventional rapid thermal anneal is observed. The overlap junction resistance is not degraded and transistors, processed exclusively with lowly doped drain junctions, show a significant performance gain. High boron (B)-pocket dose leads to good transistor short-channel effect control, overcoming the B deactivation issue. The impact of B-pocket-related counterdoping and channel-mobility degradation on device characteristics are investigated. In the presence of heavily doped substrates, band-to-band tunneling is the dominant mechanism driving the reverse-bias junction leakage and is higher than the trap-assisted tunneling contribution related to the end-of-range defects     

Investigation of the degradation of InGaAs/InP double HBTs underreverse base-collector bias stress

In this paper, we report on the degradation of DC performance of InP/InGaAs/InP double heterojunction bipolar transistors (DHBTs) during electrical stress. Devices with different sizes were investigated under highly reverse base-collector (B-C) bias stress. The increase of B-C and emitter-base (E-B) junction leakage and decrease of current gain were observed. The increase of the junction leakage for both B-C and E-B junctions was found to scale with the junction perimeters which suggests that the stress-induced damages are localized at the junction peripheries. For the devices with larger emitter periphery-to-area ratio, a more pronounced decrease of current gain due to the stress was observed. The obtained experimental data indicate that the stress-induced degradation happens in high reverse B-C bias voltage (avalanche) regime. The degradation is believed to be induced by hot carriers rather than current. A physical model is proposed to explain the experimental observations     

Leakage current mechanisms in Hydrogen-passivated fine-grain polycrystalline Silicon on insulator MOSFET's

In this paper we identify various sources of leakage current in thin-film silicon on insulator (SOI) MOSFET's made in hydrogen-passivated small-grain polycrystalline silicon. The action of a parasitic bipolar transistor that can amplify the leakage current due to the thermally generated carriers has been confirmed and characterized. A current gain (β) of more than 6 for the parasitic bipolar transistor has been experimentally measured in accumulation-mode devices, in spite of the presence of a large number of defects. This high gain is attributed to the presence of the vertical electric field, which separates the carriers, thus reducing the probability of recombination. The presence of field-enhanced generation is shown to be the cause of the observed increase in the leakage current with positive front- or back-gate bias for p-channel accumulation-mode devices. Reasonable agreement has been obtained between experimental data and theory based on field-enhanced generation due to Poole-Frenkel barrier lowering.     

Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses

The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this.     

Reliability investigation of AlGaN/GaN high electron mobility transistors under reverse-bias stress

Impact of reverse-bias stress on the reliability of AlGaN/GaN high electron mobility transistors was investigated in this paper. We found that inverse piezoelectric effect could induce noisy characteristics of stress current, and the “critical voltage” increased with the drain–source bias in the step-stress experiments. Although the degradation of the gate leakage current and drain-to-source leakage current are non-recoverable, the maximum output current can recover almost completely through electron de-trapping procedure after stress. The de-trapping activation energy was estimated to be 0.30 eV by the dynamic conductance technique. The surface morphology of the electrically stressed devices was investigated after removing the gate metallization by chemical etching, and no pits or cracks under the gate contact were observed.     

GaN基绿光LED芯片电流加速失效机理研究

采用电流加速的电应力老化方法研究GaN基绿光 LED芯片的失效机理。LED芯片在经过60 mA 电流老化424 h后,其发光效率总体趋势都是随老化时间增加而减小 ,但是小测量电流相比于大测量电 流的发光效率衰减程度更为明显。同时,在正向偏压下电流电压曲线基本没有变化,而反向 偏压下的反向 电流随老化时间的增加而快速增加。笔者认为在电应力老化作用下,随老化时间增加,有源 区的缺陷能级 增多,在正向偏压下,缺陷能级起到一个有效陷阱的作用,增加了载流子的寿命,降低了辐 射复合的几率, 使得发光效率降低,但是并没有减小正向偏压下的电流,而反向偏压时,缺陷能级起到了一 个漏电通道的作用,使得反向电流增大。     

The base current degradation of poly-emitter BJTs under AC stress

A simple model for the analysis of the ac stress effect in poly-emitter bipolar transistors is presented. Apart from the reverse-bias induced hot-carrier effects, the forward-bias recovery effect is a key factor under ac stress, it obviously suppresses the base current degradation of the device which is caused during the reverse-bias periods. In this work, we derived the relationship between the excess base current and the stress time for different ac stress conditions. This model is verified with experimental results.<>     

Inherent and stress-induced leakage in heavily doped siliconjunctions

Inherent leakage currents and leakage induced with reverse-bias stress are investigated in heavily doped emitter-base junctions of polysilicon self-aligned bipolar transistors and similar diodes. Inherent in the devices is a reverse leakage component found to have a perimeter trap-assisted tunneling component characteristic of the Si-SiO ₂ surface and evident at doping insufficient for significant band-to-band tunneling. The band-to-band phonon-assisted tunneling and avalanche leakage components are also identified. Introducing surface states through reverse-bias stress induces a Pool-Frenkel electric field enhanced generation/recombination surface leakage component. The induced and trap-assisted tunneling components are distinct. The induced component is found to saturate as available states, dependent on the peak electric field, are exhausted. Trapped charge accumulation after extensive stressing affects the electric field along the surface reducing the induced and trap-assisted tunneling leakage components     

Degradation Study of Organic Semiconductor Devices Under Electrical and Optical Stresses

Degradation due to electrical and optical stresses on organic semiconductor devices fabricated with imidazolin-5-one as an active layer is studied in this letter. It is found that while both electrical and optical stresses degrade device performance, the former leads to much faster degradation as compared with the latter. It is found that in electrical-stress degradation, the drop in current is a strong function of the charge flowing through the device during stress (charge fluence). For optical-stress degradation, it is strongly dependent on the duration of stress. It is also found that the input electrical and light energy during the stress may be annealing out some of the defects in the device and, hence, mitigating the degradation due to the applied stress.     

Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V_G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.     

Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

A deep analysis of the intrinsic junction and surface currents in power vertically diffused MOS devices with sub-micrometer channel length and thin gate oxide has been carried on after a typical reliability high temperature reverse bias (HTRB) stress. A reference set of gated diodes has also been examined in order to better understand the onset and evolution of post-stress leakage degradation. A comparison among complete MOSs, single body diodes and enriched diodes allows to highlight the role played by the point defectivity both at gate interface and in the bulk silicon close to the junction surface. We found that the typical interface defects involved in the leakage degradation are shallow traps and can be de-populated simply by a thermally activated mechanism. More specifically, the main degradation mechanism relies to band-defect-band tunneling localized at the surface drain/body junction where an intrinsic n-i-p region evolves due to a bird’s beak lateral profile of the body diffusion. We have demonstrated that the most important contribution to the activation of the precursor defect sites is given by the transverse electrical field that develops just below the SiO₂/Si interface within the n-i-p region during the stress.     

Reduction of leakage current in metal-induced lateral crystallization polysilicon TFTs with dual-gate and multiple nanowire channels

This letter addresses the leakage current in nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with multiple nanowire channels and dual-gate. Experimental results reveal that applying multiple nanowire channels improves the Ni-MILC poly-Si TFT performance. However, the leakage current of both single-gate with single-channel and multiple nanowire channels remains high (>10/sup -8/ A), because of the field emission of carriers through the poly-Si grain traps and the defects caused by Ni contamination. Applying the dual-gate structure can suppress the electrical filed in the drain depletion region, significantly reducing the leakage current of the Ni-MILC poly-Si TFT, increasing the ON/OFF ratio.     

Leakage current by Frenkel–Poole emission on benzotriazole and benzothiadiazole based organic devices

In this study three different organic semiconductors were used in the fabrication of ITO/PEDOT:PSS/Polymer:PCBM/LiF/Al configuration. Reverse current density–voltage (J_r–V) measurements of the samples were investigated to define the reverse-bias leakage current mechanisms on benzotriazole and benzothiadiazole based organic devices. Our results indicate that the J_r–V plot behaviors are given by linear dependence between In ( J_r) and V^1/2, where J_r is the reverse current density, and V is the applied voltage. This behavior is well known as the Poole–Frenkel (PF) effect where it is found to be dominating in the reverse-bias leakage current.     

Effect of the post-gate annealing on the gate reliability of AlGaN/GaN HEMTs

In this paper,we investigated the effect of post-gate annealing (PGA) on reverse gate leakage and the reverse bias reli-ability of Al0.23Ga0.77N/GaN high electron mobility transistors (HEMTs).We found that the Poole-Frenkel (PF) emission is domin-ant in the reverse gate leakage current at the low reverse bias region (Vth ＜ VG ＜ 0 V) for the unannealed and annealed HEMTs.The emission barrier height of HEMT is increased from 0.139 to 0.256 eV after the PGA process,which results in a reduction of the reverse leakage current by more than one order.Besides,the reverse step stress was conducted to study the gate reliabil-ity of both HEMTs.After the stress,the unannealed HEMT shows a higher reverse leakage current due to the permanent dam-age of the Schottky gate.In contrast,the annealed HEMT shows a little change in reverse leakage current.This indicates that the PGA can reduce the reverse gate leakage and improve the gate reliability.     

Hot-carrier effects in Hydrogen-passivated p-channel polycrystalline-Si MOSFET's

The dependence of hot-carrier effects on channel length and stress-bias voltage in hydrogen-passivated accumulation-mode p-channel polycrystalline-Si MOSFET's operating in the saturation region has been studied, Before stress, these devices exhibit a minimum value of current at VGS≈ 0 V but as VGSincreases above 0 V, they show an increase in (leakage) current due to field-enhanced generation of carriers near the drain. After stress, the current at VGS≈ 0 V increases slightly with respect to its pre-stress value. However, the current then monotonically decreases as VGSincreases above 0 V unlike the situation before stress. No change in reverse mode (source and drain reversed) characteristics and no change in the ON-state (VGS< 0 V) forward-mode characteristic was observed after stress. These observations are shown to be due to hot-carrier-induced acceptor-type interface states near the drain in forward-mode operation.     

Hot-carrier-induced deep-level defects from gated-diodemeasurements on MOSFETs

The reverse-bias current in the gated-diode configuration of hot-carrier degraded MOS devices was measured. It is shown that interface defects created by the degradation contribute predominantly to the generation current. The spatial distribution of the deep-level defects was obtained by means of device simulation     

Temperature dependence of hot-electron degradation in bipolartransistors

Degradation of the base current and current gain observed in bipolar transistors that were electrically stressed at-75, 175, and 240°C for 1000 h with a constant reverse-bias voltage applied to the emitter-base junctions is discussed. The rate of degradation was found to be temperature-dependent with a larger degradation occurring at the lower temperature. This temperature dependency is studied using an electron energy simulation technique and experimental data on degradation and postdegradation annealing. From the electron energy simulations, the number of hot electrons above a damage threshold energy was seen to increase with increasing ambient temperature at a constant reverse-bias voltage. This increase with temperature occurred because higher stress currents dominated over a reduction in the electron mean free path between collisions at higher temperatures. However, an actual degradation rate reduction at higher temperatures occurs because of simultaneous annealing of the states produced by hot electrons. A model that describes the temperature dependence of degradation and postdegradation annealing is described     

Hot electrons induced degradation in lattice-matched InAlN/GaN high electron mobility transistors

In this paper, lattice-matched Pt/Au-In_0.17Al_0.83N/GaN high electron mobility transistors (HEMTs) were fabricated, and the degradation characteristics of the gate leakage current were investigated by drain-to-source voltage (V_DS) step-stress measurements under the ON, semi-ON, and OFF stress conditions and at different temperatures, respectively. It is found that, (1) there exists a critical value of V_DS, beyond which the gate leakage current begins to increase significantly; and (2) the degradation of gate leakage current has a positive temperature coefficient, indicating that high temperature can accelerate the degradation. A hot electron model is used to explain the experimental results, emphasizing that the hot electrons from the channel can induce additional negatively charged defects at the InAlN/GaN interface, which can increase the local electrical field and introduce a thinner surface barrier and finally enhance the vertical leakage current component, leading to the current degradation.     

A new "mixed-mode" reliability degradation mechanism in advanced Si and SiGe bipolar transistors

A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward current stress and damage due to ionizing radiation. Extensive measurements and two-dimensional (2-D) simulations have been used to help understand the device physics associated with this new degradation mechanism.