离散Hopfield神经网络和联想记忆的开关电流技术实现

研究了离散Ｈｏｐｆｉｅｌｄ神经网络（ＤＨＮＮ）和联想记忆神经网络的开关电流技术实现，利用多权输入跨导，开关电流延迟器（ＳＩＤ）和可编程电流比较器（ＰＣＣ）实现了离散Ｈｏｐｉｅｌｄ神经网络，并提出了利用离散Ｈｏｐｆｉｅｌｄ神经网络实现自联想记忆时相应的开关电流电路，所提出了开关电流神经网络适宜于超大规模集成，能在低电压（如３．３Ｖ）下工作。     

A new switched current circuit fault diagnosis approach based on pseudorandom test and preprocess by using entropy and Haar wavelet transform

This paper presents a new switched current (SI) circuit fault diagnosis approach based on pseudorandom test and preprocess by using entropy and Haar wavelet transform. The proposed method has the capability to detect and identify faulty transistors in SI circuit by analyzing its time response. The use of pseudorandom sequences as a stimulate signal to SI circuit reduces the cost of testing and the overhead of the test generation circuit, and using entropy and Haar wavelet transform to preprocess the time response for feature extraction drastically improves the fault diagnosis efficiency. For both actual experiment and analysis of switched current filters in Z transform (ASIZ) simulation, a low-pass, a band-pass SI filter and a clock feed-through cancellation circuit have been used as test examples to verify the effectiveness of the proposed method. The result shows that the accuracy of fault recognition achieved is about 100% by analyzing low-frequency approximations entropy and high-frequency details entropy. Therefore, it indicates that the presented method is superior than other methods.     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

级联开关电流滤波器设计

本文提出了一种新的有源器件开关电流运算放大器(SIOA)。新元件的引入大大减化了电路的作图,十分便于开关电流(SI)电路的分析和综合。以开关电容(SC)电路为原型,导出了若干新的全极点和椭圆(二阶或三阶)SI电路。这些电路既可作为滤波节单独使用,也可用于级联设计以实现高阶转移函数。为了说明设计方法,给出了一个五阶SI低通滤波器设计例子。     

多功能开关电流双二次滤波器生成

本文提出了一个具有差分输出的通用开关电流一阶积木块，并阐述了采用该积木块生成多功能ＳＩ滤波器的系统方法，以单放大器，两放大器和三放大器有源ＲＣ或ＳＣ网络为原型，系统地导出了一系列新的ＳＩ双二次结构，生成的所有ＳＩ电路均可在单一积木块上同时获得低通、高通和带通滤波功能，这些电路的灵敏度低，且为纯ＭＯＣ管结构，非常适合于数字ＣＭＯＳ工艺集成。     

Modelling,design and stability analysis of an improved SEPIC converter for renewable energy systems

In this paper, a detailed modelling and analysis of a switched inductor (SI)-based improved single-ended primary inductor converter (SEPIC) has been presented. To increase the gain of conventional SEPIC converter, input and output side inductors are replaced with SI structures. Design and stability analysis for continuous conduction mode operation of the proposed SI-SEPIC converter has also been presented in this paper. State space averaging technique is used to model the converter and carry out the stability analysis. Performance and stability analysis of closed loop configuration is predicted by observing the open loop behaviour using Nyquist diagram and Nichols chart. System was found to stable and critically damped.     

开关电流技术：一种新的模拟抽样数据处理方法

开关电流（ＳＩ）技术是一种新的模拟抽样数据处理技术，介绍了开关电流电路的基本单元结构，讨论了目前开关电流技术中存在的问题及其解决方法。对开关电流技术与开关电容技术的一些基本特征进行了比较，ＳＩ技术不仅结构简单，而且与标准ＣＭＯＳ工艺兼容，可望替代开关电容电路。     

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2-μm n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique     

SWITCHED-CURRENT FILTER DESIGN USING CASCADED SECTIONS

A new analogue sampled-data active device, named as a switched-current operationalamplifier (SIOA), is presented. The use of active circuit elements may simplify drawing the circuitdiagram significantly greatly and may permit easier analysis and synthesis of SI networks. Anumber of all pole and elliptic (second-or third-order) switched-current (SI) filters are derivedfrom the switched capacitor prototypes. These can be used as simple self-contained filters or asfilter sections in the cascaded realizations of a higher order transfer functions. To illustrate theapproach, a fifth-order low-pass filter is designed.     

New CMOS linear transconductor

A new transconductor is proposed which uses a bias feedback technique and has a simple configuration and a good high-frequency performance. The proposed transconductor is tunable by adjusting the bias current, and suitable for application to highly linear continuous-time filters. Experimental results show that the total harmonic distortion (THD) of the output current is less than 1% for the differential/single-ended input signals of up to 6.0 V/4.3 V (peak-to-peak) when the supply voltages are +or-5 V.<>     

High-frequency switched-capacitor filter using unity-gain buffers

The implementation of high-frequency switched-capacitor filters using unity-gain amplifiers in a balanced configuration is described. The effect of parasitic capacitances is analyzed for different structures, single-ended and balanced. Experimental results from a third-order elliptic filter integrated in a standard NMOS process are presented.     

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-mum CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution (<12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.     

High-selectivity single-ended and balanced bandpass filters using ring resonators and coupled lines loaded with multiple stubs

High-selectivity single-ended and balanced bandpass filters (BPFs) using dual-mode ring resonators and coupled lines loaded with multiple stubs are proposed in this paper. With the help of the loaded short-circuited and open-circuited stubs, six deep transmission zeros (TZs) from 0 to 2f₀ (f₀: center frequency of the passband) can be realized in both of single-ended and balanced BPFs to improve the stopband suppressions. The functions of the loaded short/open stubs and calculated analysis of TZs’ positions have been presented. For further demonstration, two examples of single-ended BPF and balanced BPF with high common-mode suppression are designed and fabricated, whose center frequencies are both at 2.1 GHz. Their measured 3-dB fractional bandwidths are 23.7% and 24.7% (differential-mode), respectively. The simulated results and measurements of these two filters are in good agreement.     

Analog wavelet transform using multiple-loop feedback switched-current filters and simulated annealing algorithms

A new approach for implementing continuous wavelet transform (CWT) based on multiple-loop feedback (MLF) switched-current (SI) filters and simulated annealing algorithms (SAA) is presented. First, the approximation function of wavelet bases is performed by employing SAA. This approach allows for the circuit implementation of any other wavelets. Then the wavelet filter whose impulse response is the wavelet approximation function is designed using MLF architectures, which is constructed with SI differentiators and multi-output cascade current source circuits. Finally, the CWT is implemented by controlling the clock frequency of wavelet filter banks. Simulation results of the proposed circuits and the filter banks show the advantages of such new designs.     

Prospect of the future of switched-current circuits with regard to future CMOS technologies

Low supply voltages in modern CMOS technologies are expected to reduce the maximum resolution of analog to digital converters in voltage mode operation. This paper outlines the functionality and possibilities of switched current (SI) circuit techniques in medium accuracy ΔΣ modulators. Starting with the presentation of different kinds of switched current cells, this paper gives an overview about the simulated performance followed by a comparison of switched current and switched capacitor circuits. A prospect of the future of switched current circuits with regard to future CMOS technologies is given.     

A new swarm-SVM-based fault diagnosis approach for switched current circuit by using kurtosis and entropy as a preprocessor

This paper presents a new fault diagnosis method for switched current (SI) circuits. The kurtoses and entropies of the signals are calculated by extracting the original signals from the output terminals of the circuit. Support vector machine (SVM) is introduced for fault diagnosis using the entropies and kurtoses as inputs. In this technique, a particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits. The proposed method can identify faulty components in switched current circuit. A low-pass SI filter circuit has been used as test beached to verify the effectiveness of the proposed method. The accuracy of fault recognition achieved is about 97 % although there are some overlapping data when tolerance is considered. A comparison of our work with Long et al. (Analog Integr Circuit Signal Process 66:93–102, 2011), which only used entropy as a preprocessor, reveals that our method performs well in the part of fault diagnostic accuracy.     

基于改进差分进化算法的连续小波变换电路

提出一种基于改进差分进化算法和开关电流微分器的连续小波变换实现的新方法。引入混沌初始化种群、自适应变异和指数递增交叉概率因子,提高差分进化算法的收敛速度和精度,构造小波函数逼近模型,并利用改进差分进化算法,求得小波逼近函数及频域传递函数。采用开关电流微分器作为基本单元,设计冲激响应为小波逼近函数的开关电流滤波器组,通过调节小波滤波器的时间常数,获得多尺度小波函数,实现连续小波变换。实验结果表明该方法可行。     

A Comparison of Two Switched Current Differentiators at Extremely Low Current Level

We are presenting comparative studies on two switched current (SI)differentiators; one is a classical version, the other is a cumulativeversion. Both are applied to smart pixel time-domain differentiation. Inboth differentiators, the differentiation is calculated by subtracting theinstantaneous photocurrent from a previously sampled one. The key issue inthis case is to obtain accuracy even with an extremely low current level(from pA to nA). The operability of both SI memories is verified throughchip tests. Within an optical input dynamic range of five decades and aminimum level of 2 Lux (1pA in current), the maximum current reproductionerror rate is 10% for the first one and 6% for the second.Furthermore, the cumulability of the second version is also confirmed by ourtests.     

Analog VLSI implementation of wavelet transform using switched-current circuits

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.     

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.