Stress Controlled Silicon Nitride Thin Film Deposited by Plasma Enhanced Chemical Vapour Deposition

SiN, films are deposited on silicon wafers through plasma enhanced chemical vapor deposition （PECVD）. The relationship between the film stress and deposition factors is investigated. It is found that low stress films would be obtained by adjusting the ratio of low frequency（LF） power to high frequency（HF） power pulse time or the chamber pressure. The best of the two methods to control stress in the film is changing the percentage of LF power pulse time. The low stress condition is achieved when the percentage of low frequency power pulse time in total time（LF and HF pulse time） is close to 40%, The low stress cantilever of tunable vertical cavity surface emitting laser is obtained by using this deposition condition,     

Preparation and characterization of transparent conducting ZnO:W films by DC magnetron sputtering

Tungsten-doped zinc oxide（ZnO:W） films with low resistivity and high transmittance were successfully deposited on glass substrates by direct current magnetron sputtering at low temperature.The deposition pressure is varied from 12 to 21 Pa.The X-ray diffraction results show that all of the deposited films are polycrystalline and have a hexagonal structure with a preferred c-axis orientation.The crystallinity,morphologies and resistivity of ZnO:W films greatly depend on deposition pressure while the optical properties including optical transmittance, optical band gap as well as refractive index are not sensitive to deposition pressure.The deposited films with an electrical resistivity as low as 1.5×10^-4Ω·cm,sheet resistance of 6.8Ω/□and an average transmittance of 91.3% in the visible range were obtained at a deposition pressure of 21 Pa and sputtering power of 130 W.     

厚度对柔性衬底上制备的ZnO:Zr透明导电薄膜性能的影响

Transparent conducting zirconium-doped zinc oxide （ZnO：Zr） thin films with high transparency, low resistivity and good adhesion were successfully prepared on water-cooled flexible substrates （polyethylene glycol terephthalate, PET） by RF magnetron sputtering. The structural, electrical and optical properties of the films were studied for different thicknesses in detail. X-ray diffraction （XRD） and scanning electron microscopy （SEM） revealed that all the deposited films are polycrystalline with a hexagonal structure and a preferred orientation perpendicular to the substrate. The lowest resistivity achieved is 1.55 × 10-3 Ω·cm for a thickness of 189 nm with a Hall mobility of 17.6 cm2/（V·s） and a carrier concentration of 2.15×1020 cm-3. All the films present a high transmittance of above 90% in the wavelength range of the visible spectrum.     

衬底温度对In掺杂CdO薄膜的结构和性能的影响

Transparent indium-doped cadmium oxide（In-CdO） thin films were deposited on quartz glass substrates by pulsed laser deposition（PLD） from an ablating Cd-In metallic target.The effect of substrate temperature on the structural,optical and electrical properties of In-doped CdO thin films were studied in detail.The optical transmittance of In doped CdO films are obviously influenced by the substrate temperature.All films exhibit a transmittance higher than 75%in the visible region.More significantly,In-doping leads to an evident widening of optical band gap from 2.56 to 2.91 eV;and the increase in optical band gap is found to depend on the deposition temperature.It is also seen that the electrical properties of these films strongly depend on the substrate temperature. The In-CdO thin film grown at 300℃has low resistivity(1.15×10^-4Ω·cm),high carrier concentration(5.35×10²⁰ cm^-3),and high mobility（101.43 cm²/（V·s））.     

有源层溅射温度对非晶铟镓锌氧薄膜晶体管电学特性的影响

The effect of active layer deposition temperature on the electrical performance of amorphous InGaZnO （a-IGZO） thin film transistors （TFTs） is investigated. With increasing annealing temperature, TFT performance is firstly improved and then degraded generally. Here TFTs with best performance defined as ＂optimized-annealed＂ are selected to study the effect of active layer deposition temperature. The field effect mobility reaches maximum at deposition temperature of 150℃ while the room-temperature fabricated device shows the best subthreshold swing and off-current. From Hall measurement results, the carrier concentration is much higher for intentional heated a-IGZO films, which may account for the high off-current in the corresponding TFT devices. XPS characterization results also reveal that deposition temperature affects the atomic ratio and Ols spectra apparently. Importantly, the variation of field effect mobility of a-IGZO TFTs with deposition temperature does not coincide with the tendencies in Hall mobility of a-IGZO thin films, Based on the further analysis of the experimental results on a-IGZO thin films and the corresponding TFT devices, the trap states at front channel interface rather than IGZO bulk layer properties may be mainly responsible for the variations of field effect mobility and subthreshold swing with IGZO deposition temperature.     

Preparation and characterization of cubic lattice ZnS：Na Films with （111） preferred orientation

ZnS：Na thin films with （111） preferred orientation were deposited on glass substrates by vacuum evaporation method. The as-prepared films were annealed in flowing argon at 400--500 ℃ to improve the film crystallinity and electrically activate the dopants. The structural, optical and electrical properties of ZnS：Na films are investigated by X-ray diffrac- tion （XRD）, photoluminescence （PL）, optical transmittance measurements and the four-point probe method. Results show that the as-prepared ZnS：Na films are amorphous, and exhibit （111） preferred orientation after annealing at 400 --500 ℃. The PL emissions at 414 nm and 439 nm are enhanced due to the increase of the intrinsic defects induced by the thermal annealing. However, all the samoles exhibit high resistivitv due to the heavy self-compensation.     

Stress control of silicon nitride films deposited by plasma enhanced chemical vapor deposition

Stress controllable silicon nitride(Si Nx) films deposited by plasma enhanced chemical vapor deposition(PECVD) are reported. Low stress Si Nx films were deposited in both high frequency(HF) mode and dual frequency(HF/LF) mode. By optimizing process parameters, stress free(-0.27 MPa) Si Nx films were obtained with the deposition rate of 45.5 nm/min and the refractive index of 2.06. Furthermore, at HF/LF mode, the stress is significantly influenced by LF ratio and LF power, and can be controlled to be 10 MPa with the LF ratio of 17% and LF power of 150 W. However, LF power has a little effect on the deposition rate due to the interaction between HF power and LF power. The deposited Si Nx films have good mechanical and optical properties, low deposition temperature and controllable stress, and can be widely used in integrated circuit(IC), micro-electro-mechanical systems(MEMS) and bio-MEMS.     

P-type ZnO thin films prepared by in situ oxidation of DC sputtered Zn3N2:Ga

The feasibility of a new fabrication route for N and Ga codoped p-type ZnO thin films on glass substrates, consisting of DC sputtering deposition of Zn3N2:Ga precursors followed by in situ oxidation in high purity oxygen, has been studied. The effects of oxidation temperature on the structural, optical and electrical properties of the samples were investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), optical transmittance and Hall effect measurements. The results were compared to a control film without Ga. XRD analyses revealed that the Zn3N2 films entirely transformed into ZnO films after annealing Zn3N2 films in oxygen over 500 ℃ for 2 h. Hall effect measurements confirmed p-type conduction in N and Ga codoped ZnO films with a low resistivity of 19.8 Ω?cm, a high hole concentration of 4.6E18 cm3 and a Hall mobility of 0.7 cm2/(V s). These results demonstrate a promising approach to fabricate low resistivity p-type ZnO with high hole concentration.     

Growth and microstructure properties of microcrystalline silicon films deposited using jet-ICPCVD

Microcrystalline silicon films were deposited at a high rate and low temperature using jet-type inductively coupled plasma chemical vapor deposition(jet-ICPCVD).An investigation into the deposition rate and microstructure properties of the deposited films showed that a high deposition rate of over 20 nm/s can be achieved while maintaining reasonable material quality.The deposition rate can be controlled by regulating the generation rate and transport of film growth precursors.The film with high crystallinity deposited at low temperature could principally result from hydrogen-induced chemical annealing.     

Nano-ZnO film preparation at low temperature and the optical indices calculation

The refractive indices of thin films based on Kramers-Kronig theory are corrected. And the correction theory is used to determine the optical indices of nano-ZnO thin films prepared by low temperature sol-gel method. The calculated results indicate that in the visible （Vis） range, the refractive indices of nano-ZnO thin films exhibit a slight abnormal dispersion, while in the ultraviolet （UV） region, the refractive indices increase with wavelengths increasing （normal dispersion）. But the refractive indices show complex change near the absorption edge. The maximum refractive index （1.95） of nano-ZnO thin films within UV range at low temperature annealing is much lower than that of the films annealed at high temperature. The absorption and refractive indices are closely related to the defects in nano-ZnO thin films.     

利用物理气相淀积工艺制备的HfTaON薄膜热力学稳定性研究

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope （HRTEM） and X-ray photoelectron spectroscopy （XPS）. The results indicate that the magnetron-sputtered HfTaON films on Si substrate are not stable during the post-deposition annealing （PDA）. HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfraON and Si substrate may effectively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric＇s equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric＇s equivalent oxide thickness.     

PVT法CdS单晶生长

Based on the physical vapor transport （PVT） method, the growth of large-size CdS crystals inside a vertical semi-closed tube is studied. Firstly, in order to ensure 1D diffusion-advection transport, multi-thin tubes are used in the growth tube. The XRD spectra of the CdS crystal grown in this configuration indicates that the crystal quality has clearly been improved, where the FWHM is 58.5 arcsec. Secondly, theoretical and experimental growth rates under different total pressures are compared; the results show that the experiential growth rate equation is valid for our semi-tube growth, and it could be used to estimate the growth rate and maximum growth time under different total pressures.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

适用于双金属栅集成的TaN湿法腐蚀

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

基于非线性DAC的高速直接数字频率合成器

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.     

掉电后SRAM防数据残留物理攻击的安全策略

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered- off static random access memory （SRAM）. Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.     

一种应用于频率综合器的全差分电荷泵的设计与噪声分析

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.