共查询到19条相似文献，搜索用时 57 毫秒
1.
2.
为了详细地了解纳米MOS电路中单粒子瞬变电荷收集机理,利用ISETCAD软件仿真二维模拟0.18μm NMOS的单粒子瞬态脉冲。通过进行三种不同的电路连接方式和不同的粒子注入位置的仿真,得到了一系列单粒子瞬态电流脉冲(SET)与时间的关系曲线。分析了不同电路连接方式和注入位置对SET的峰值和脉宽的影响。为下一步建立SET的精确模型进行SET效应的模拟做基础的研究。 相似文献
3.
摘要：为了详细的了解纳米MOS电路中单粒子瞬变电荷收集机理,利用ISETCAD软件仿真二维模拟0.18um NMOS的单粒子瞬态脉冲。通过进行三种不同的电路连接方式和不同的粒子注入位置的仿真,得到了一系列单粒子瞬态电流脉冲（SET）与时间的关系曲线。分析了不同电路连接方式和注入位置对SET的峰值和脉宽的影响。为下一步建立SET的精确模型进行SET效应的模拟做基础的研究。 相似文献
4.
本文提出了一种在线表征负偏压温度不稳定性(NBTI,negative bias temperature insta-bility)退化的方法--直接隧道栅电流表征法(DTGCM,DT Gate Current Method)。用这种方法可以得到NBTI应力诱生在超薄栅氧化层中的缺陷密度(包括氧化层体陷阱密度和界面态密度),并得到PMOSFET器件阈值电压的漂移(ΔVth)信息。这种方法可以有效避免NBTI恢复效应的影响。 相似文献
5.
6.
随着MOS器件尺寸缩小,可靠性效应成为限制器件寿命的突出问题.PMOS晶体管的负偏压温度不稳定性（NBTI）是其中关键问题之一.NBTI效应与器件几何机构密切相关.本文对不同宽长比的65nm工艺PMOSFET晶体管开展了NBTI试验研究.获得了NBTI效应引起的参数退化与器件结构的依赖关系,试验结果表明65nm PMOSFET的NBTI损伤随沟道宽度减小而增大.通过缺陷电荷分析和仿真的方法,从NBTI缺陷产生来源和位置的角度,揭示了产生该结果的原因.指出浅槽隔离（STI）区域的电场和缺陷电荷是导致该现象的主要原因.研究结果为器件可靠性设计提供了参考. 相似文献
7.
单粒子瞬态脉冲宽度是评价电子系统软错误率的重要参数之一。针对0.13 μm、部分耗尽型绝缘体上硅(PDSOI)工艺下的反相器链,解析地计算了反相器中产生的单粒子瞬态脉冲宽度,仿真了产生的单粒子瞬态脉冲在反相器链中传播时的临界脉冲宽度和传输率随级数变化情况。仿真结果表明,单粒子瞬态脉冲宽度的大小在几十皮秒到几百皮秒之间,反相器链的级数对临界脉冲宽度和传输率影响较大。最后仿真得到在输入单粒子瞬态脉冲宽度较小时,建立保持时间与输入脉冲宽度有关。该结果有利于电气掩蔽建模和锁存掩蔽建模准确性的提高。 相似文献
8.
9.
10.
验证SiGe BiCMOS工艺线性器件的单粒子瞬态（Single Event Transient,SET）效应敏感性,选取典型运算放大器THS4304和稳压器TPS760进行了脉冲激光试验研究。试验中,通过能量逐渐逼近方法确定了其诱发SET效应的激光阈值能量,并通过逐点扫描的办法分析了器件内部单粒子效应敏感区域,并在此基础上分析了脉冲激光能量与SET脉冲的相互关系,获得了单粒子效应截面,为SiGe BiCMOS工艺器件在卫星电子系统的筛选应用以及抗辐射加固设计提供数据参考。 相似文献
11.
The effect of negative bias temperature instability(NBTI) on a single event transient(SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations.The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter;but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter.Based on this study,for the first time we ... 相似文献
12.
13.
14.
Technology scaling results in the propagation-induced pulse broadening and quenching (PIPBQ) effect become more noticeable. In order to effectively evaluate the soft error rate for combinational logic circuits, a soft error rate analysis approach considering the PIPBQ effect is proposed. As different original pulse propagating through logic gate cells, pulse broadening and quenching are measured by HSPICE. After that, electrical effect look-up tables (EELUTs) for logic gate cells are created to evaluate the PIPBQ effect. Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm. Further, by propagating pulses on these paths to simulate fault injection, the PIPBQ effect on these paths can be quantified by EELUTs. As a result, the soft error rate of circuits can be effectively computed by the proposed technique. Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method. 相似文献
15.
The shrinking silicon feature size causes the continuous increment of the aging effect due to the negative bias temperature instability (NBTI), which becomes a potential stopper for IC development. As the basis of circuit-level aging protection, an efficient aging critical-gate identification method is crucially required to select a set of gates for protection to guarantee the normal lifetime of the circuits. The existing critical-gate identification methods always depend on a critical path set which contains so many paths that its generation procedure requires undesirable CPU runtime; furthermore, these methods can achieve a better solution with taking account of the topological connection. This paper proposes a time-efficient critical gates identification method with topological connection analysis, which chooses a small set of critical gates. Experiments over many circuits of ITC99 and ISCAS benchmark demonstrate that, to guarantee the normal lifetime (e.g., 10 years) of each circuit, our method achieves a 3.97x speedup and saves as much as 27.21% area overhead compared with the existing methods. 相似文献
16.
NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction. 相似文献
17.
随着集成电路芯片制造工艺进入纳米阶段,电路可靠性问题变得越来越严重,以负偏置温度不稳定性效应为代表的电路老化也逐渐成为影响其性能的重要因素.基于老化预测的精确性和传感器功能的多样性,提出了一种抗老化、可编程的老化预测传感器.其中稳定性检测器部分利用反馈回路解决了浮空点问题,同时整合了锁存器部分,实现了对老化预测结果的自动锁存,从而增加了老化预测的精确度,减小了一定的面积开销.最后通过HSPICE模拟器仿真验证了该传感器的优越性,且与经典结构相比降低了约21.43％的面积开销. 相似文献
18.
NBTI导致的晶体管老化成为影响电路稳定性的主导因素,同时,降低电路的泄漏功耗是电路设计的目标之一。多米诺电路广泛应用在高性能集成电路中。本文提出了一种多米诺电路用来抑制NBTI引起的多米诺电路衰退并同时降低待机模式下的泄漏电流。在待机模式下,利用2个晶体管将标准多米诺电路的动态节点和输出节点同时上拉为电源电平,从而将保持器和输出反相器中的pMOS晶体管同时置为NBTI的恢复模式。使用全0输入向量和其中增加的一个晶体管的堆栈效应降低待机模式下多米诺电路的泄漏电流。实验表明针对NBTI效应,该方法降低了最多33%的性能衰退,并同时减少了最多79%的泄漏电流。 相似文献
